AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.3.1.3.1. JESD204B IP Core

The JESD204B IP core is configured in duplex (with TX and RX data paths), non-bonded mode with the following parameter configuration:

Table 7.  JESD204B IP Core Parameter Configuration

Parameter

Value

Description

Subclass

1

Subclass mode.

L

4

Number of lanes per converter device.

M

2

Number of converters per device.

F

1

Number of octets per frame.

S

1

Number of transmitted samples per converter per frame.

N

14

Number of conversion bits per converter.

N’

16

Number of transmitted bits per sample.

K

32

Number of frames per multiframe.

CS

0

Number of control bits per conversion sample.

CF

0

Number of control words per frame clock period per link.

HD

0

High Density user data format.

SCR

Off

Enable scramble.

The JESD204B IP base core connects to the ARM HPS via the Avalon-MM bridge. There are two separate Avalon-MM ports for the JESD204B IP core:

  • Base core TX data path—for dynamic reconfiguration of the TX CSR parameters.
  • Base core RX data path—for dynamic reconfiguration of the RX CSR parameters.

The ARM® HPS writes to the JESD204B IP core CSR during a dynamic reconfiguration operation. The software instructions to execute dynamic reconfiguration of the JESD204B IP core are described in the User Commands section.

To customize the JESD204B IP core parameters to meet your specifications, follow the instructions in the Modifying JESD204B IP Core Parameters section.

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