AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

Download PDF
ID 683776
Date 12/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.8.3.1. Editing the Qsys Project

  1. Open the top level Qsys project (jesd204b_ed_soc.qsys) as per the instructions in the Qsys system section.
  2. Each JESD204B link is represented by a single jesd204b_subsystem instantiation. To implement multi-links in Qsys, duplicate the jesd204b_subsystem instantiations. In the System Contents tab, right-click on the jesd204b_subsystem_0 module and select Duplicate. This duplicates the jesd204b_subsystem_0 module to a new module called jesd204b_subsystem_1.
  3. Connect the jesd204b_subsystem_1 ports as shown in the table below. Any ports not described in the table below should be exported. To export a port, double-click on the Double-click to export label in the Export column of the System Contents tab.
    Table 20.  Port Connections of jesd204b_subsystem_1 Module

    Ports of jesd204b_subsystem_1 Module

    Connection

    device_clk

    device_clk.clk

    do_not_connect_reset_0

    mgmt_clk.clk_reset

    do_not_connect_reset_1

    mgmt_clk.clk_reset

    do_not_connect_reset_2

    mgmt_clk.clk_reset

    frame_clk

    frame_clk.clk

    jesd204b_jesd204_rx_int

    hps_0.f2h_irq0

    ILC.irq

    jesd204b_jesd204_tx_int

    hps_0.f2h_irq0

    ILC.irq

    link_clk

    link_clk.clk

    mgmt_clk

    mgmt_clk.clk

    mgmt_reset

    mgmt_clk.clk_reset

    mm_bridge_s0

    fpga_only_master.master

    mm_bridge_0.m0

    reset_seq_irq

    hps_0.f2h_irq0

    ILC.irq

    reset_seq_pll_reset

    Do not connect

    reset_seq_reset_in0

    mgmt_clk.clk_reset
  4. Adjust the IRQ port count of the ILC module to accommodate new interrupt ports of the jesd204b_subsystem_1 module. Double-click the ILC module in the System Contents tab. In the ILC module Parameters tab, adjust the IRQ_PORT_COUNT parameter to 9.
  5. Adjust the interrupt priorities of the interrupt ports (for example, jesd204b_jesd204_rx_int , jesd204b_jesd204_tx_int, reset_seq_irq) of the new jesd204b_subsystem_1 module as necessary to meet your system specifications. Click on the priority number of the relevant interrupt ports in the IRQ column of the System Contents tab and edit accordingly. The lower the number, the higher the priority.
  6. Assign the address map of the jesd204b_subsystem_1 module. Refer to the Top Level Qsys Address Map section for more details on the top level Qsys project address map. Bits 16-17 of the Avalon-MM bridge (0x0004_0000 base address) indicate the link number. Assign the address map of the jesd204b_subsystem_1 module as shown in the figure below.
    Figure 8. Multi-Link Address Map

    Notice that bits 16-17 of the address map denote the link indicator. For subsequent links, increment the link indicator accordingly. Up to 4 links can be supported in this manner.

    Attention: Do not exceed the maximum number of links (4) that the address map can support.
  7. Repeat steps 2 – 6 for subsequent links in your design.
  8. Click Generate HDL to generate the HDL files needed for Quartus compilation.
  9. After the HDL generation completes, click Finish to save your Qsys settings and exit the Qsys window.
Level Two Title