AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.7.3. Software Interrupt Service Routines (ISR)

One key feature of the ARM® HPS control unit is the ability to handle interrupt requests (IRQ) from peripherals via ISR. The reference design main.c source code defines ISRs for the following peripherals:

  • JESD204B IP core TX base layer
  • JESD204B IP core RX base layer
  • SPI master module

The ISRs in the reference design main.c source code is a very basic routine that performs these two tasks:

  • Clear interrupt request (IRQ) error flag.
  • Print error type and message (for JESD204B IP core TX and RX base layer ISR only).

The error types and messages printed by the JESD204B IP core TX and RX base layer ISRs respectively are listed below.

Error types printed by the JESD204B IP core TX base layer ISR:

  • SYNC_N error
  • SYSREF LMFC error
  • DLL data invalid error
  • Transport layer data invalid error
  • SYNC_N link reinitialization request
  • Transceiver PLL locked error
  • Phase compensation FIFO full error
  • Phase compensation FIFO empty error

Error types printed by the JESD204B IP core RX base layer ISR:

  • SYSREF LMFC error
  • DLL data ready error
  • Transport layer data ready error
  • Lane deskew error
  • RX locked to data error
  • Phase compensation FIFO full error
  • Phase compensation FIFO empty error
  • Code group synchronization error
  • Frame alignment error
  • Lane alignment error
  • Unexpected K character
  • Not in table error
  • Running disparity error
  • Initial Lane Alignment Sequence (ILAS) error
  • DLL error reserve status
  • ECC error corrected
  • ECC error fatal

The error types correspond to the tx_err, rx_err0, and rx_err1 status registers in the JESD204B IP core TX and RX register maps respectively. The printing of interrupt error messages to the App Console window is controlled by the PRINT_INTERRUPT_MESSAGES parameter in the main.h header file. Set to ‘1’ (default) to print error messages, else set to ‘0’. Refer to the Software Parameters section for more details. Modify the ISRs in the source code to customize the interrupt handling response to your system specifications.

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