AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.2.3. Compiling the HDL and Programming the Board

  1. Extract the reference design from the reference design ZIP file (jesd204b_av_soc_ref_design.zip).
  2. Launch the Quartus® Prime software.
  3. On the File menu, click Open Project.
  4. Navigate to your project directory and select the Quartus project archive file (jesd204b_ed.qar). Click Open.
  5. In the Restore Archived Project window, verify that the archive file name is jesd204b_ed.qar and set the destination folder to the destination folder of your choice. Click OK. The Quartus project opens in the Quartus window.
  6. To compile the HDL, navigate to the Processing menu and select Start Compilation. The Quartus software compiles the design and indicates the compilation status in the Tasks panel.
  7. After compilation is done, you are ready to program the FPGA device with the programming file. Navigate to the Tools menu and click Programmer.
  8. In the Programmer window, click Add File.
  9. In the Select Programming File window, navigate to <your project directory> /output_files/jesd204b_ed.sof and click Open.
  10. Verify that all the hardware setup options are set correctly to your system configurations.
  11. Click Start to download the file into the Arria V SoC device on the development board. Alternatively, if you want to use the pre-generated golden programming file, skip the Quartus compilation in step 6. In step 9, select <your project directory> output_files/jesd204b_ed_golden.sof and proceed accordingly.

After programming the Arria V SoC device on the development board, the system needs to be initialized via software before the JESD204B link can be fully active.

Attention: Do not skip this initialization step. The JESD204B link will not function correctly without software link initialization.
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