AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

Download PDF
ID 683776
Date 12/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.2.4. Setting up the Software Command Line Environment

  1. Create a software workspace in a project directory of your choice. For ease of reference, this document will assume the software workspace name of <your project directory> /software.
  2. Launch the SoC EDS ARM® DS-5 Altera Edition tool.
  3. In the Select a workspace dialog box, navigate to the software workspace, <your project directory> /software and click OK.
  4. Import the software archive project into your workspace. On the File menu, click Import.
  5. In the Import/Select window, select General > Existing Projects into Workspace and click Next >.
  6. In the Import/Import Projects window, check the Select archive file radio button.
  7. Browse to the software archive project location, select the archive project file, jesd204b_soc_baremetal_gnu.tar.gz and click OK. The software archive project file is in the location where you unzipped the reference design, jesd204b_av_soc_ref_design.zip.
  8. Verify that the jesd204b_soc_baremetal_gnu check box is checked in the Projects panel and click Finish. The ARM® DS-5 tool restores the archived software project into your workspace.
  9. In the Project Explorer tab of the main Eclipse window, expand the jesd204b_soc_baremetal_gnu project file list and verify that you see all the files listed in the Reference Design Files section.
  10. To compile the source code, right-click on the jesd204b_soc_baremetal_gnu project in the Project Explorer tab and select Build Project. This action executes the software build project Makefile.
  11. When recompiling the source code after the first compile, right-click on the jesd204b_soc_baremetal_gnu project and select Clean Project before building the project. This clears the project workspace of object files and other project executables from the previous project build.
  12. Whenever you add or remove any *.c source files from the project, in addition to adding or removing the file from the Project Explorer window, you must update the source file list in the software build project Makefile accordingly. To update the source file list in the Makefile, double-click the Makefile file under the jesd204b_soc_baremetal_gnu project in the Project Explorer tab. In the Makefile editor window, locate the 'EXAMPLE_SRC' variable and add or remove your *.c source file from the list. Save the file and proceed to build the project.
  13. View the build project log in the Console tab and verify that there are no errors during the build project operation.
  14. To download the project executable file to the ARM® HPS and execute the code in semi-hosting debug mode, right-click on the jesd204b_soc_baremetal_gnu project in the Project Explorer tab and select Debug As > Debug Configurations.
  15. In the Debug Configurations window, on the left panel, select DS-5 Debugger > jesd204b_soc_baremetal_gnu. On the right panel, under the Connection tab, in the Select target panel, select Arria V SoC > Bare Metal Debug > Debug Cortex-A9_0. Ensure that all the other connections settings in the Connection tab are set according to your system configurations.
  16. Click Debug. The tool downloads the executable code onto the ARM® HPS and launches the Debugger interface.
  17. Execution of the code is halted on the first executable line of the main.c code. To continue execution without interruption until the end of the code, click the Continue button in the Debug Control window. To step through the code line by line, use the stepping buttons in the Debug Control window.

The App Console window is the main user interface portal that you can view printed messages and enter commands to the main execution code.

Figure 2.  ARM® DS-5 - App Console GUI

The main execution code executes the JESD204B link initialization sequence and prints a command prompt for you to enter commands to the ARM® HPS. View the printed messages from the JESD204B link initialization sequence in the App Console window. Verify that the link is initialized successfully and the TX/RX status registers display the expected values. Tables below describe the expected values of the link status register report.

Table 3.  TX Status 0 Register

Bit

Name

Description

Expected Binary Value

[0]

SYNC_N value

0: Receiver is not in sync

1: Link is in sync

1

[2:1]

Data Link Layer (DLL) state

00: Code Group Synchronization (CGS)

01: Initial Lane Alignment Sequence (ILAS)

10: User data mode

11: D21.5 test mode

10

Table 4.  RX Status 0 Register

Bit

Name

Description

Expected Binary Value

[0]

SYNC_N value

0: Receiver is not in sync

1: Link is in sync

1

Others

—

—

Don’t care

The code also reports the status of the pattern checker comparison. Any pattern checker errors that occur during the initialization period is flagged to the console window. Verify that the console displays this message to indicate no pattern checker errors were detected: 

INFO: No pattern checker error detected on link 0
Related Information
Level Two Title