5G Polar Intel® FPGA IP User Guide

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ID 683766
Date 3/31/2023
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Document Table of Contents
Document Table of Contents x
1. About the 5G Polar Intel® FPGA IP 2. Getting Started with the 5G Polar Intel® FPGA IP 3. Designing with the 5G Polar Intel® FPGA IP 4. 5G Polar Intel® FPGA IP Functional Description 5. 5G Polar IP User Guide Archive 6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide
1. About the 5G Polar Intel® FPGA IP x
1.1. 5G Polar Intel® FPGA IP Features 1.2. 5G Polar Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G Polar Intel® FPGA IP 1.4. 5G Polar IP Performance and Resource Utilization
2. Getting Started with the 5G Polar Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G Polar IP Timeout Behavior
3. Designing with the 5G Polar Intel® FPGA IP x
3.1. 5G Polar IP Directory Structure 3.2. Generating a 5G Polar IP 3.3. Simulating the 5G Polar IP with RTL Simulators 3.4. Simulating the 5G Polar IP with MATLAB 3.5. Simulating the 5G Polar IP with the C-model
3.3. Simulating the 5G Polar IP with RTL Simulators x
3.3.1. Simulation Results for the 5G Polar IP
4. 5G Polar Intel® FPGA IP Functional Description x
4.1. 5G Polar IP Signals 4.2. 5G Polar IP Throughput and Latency
1. About the 5G Polar Intel® FPGA IP
2. Getting Started with the 5G Polar Intel® FPGA IP
3. Designing with the 5G Polar Intel® FPGA IP
4. 5G Polar Intel® FPGA IP Functional Description
5. 5G Polar IP User Guide Archive
6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide

3.2. Generating a 5G Polar IP

To include the IP in a design, generate the IP in the Intel® Quartus® Prime software. Or optionally, you can generate a design example that includes the generated IP, a C model, a MATLAB model, and simulation scripts.
  1. Create a New Intel® Quartus® Prime project
  2. Open IP Catalog.
  3. Select DSP > FEC > 5G Polar and click Add
  4. Enter a name for your IP variant and click Create.
    The name is for both the top-level RTL module and the corresponding .ip file.
    The parameter editor for this IP appears.
  5. Choose your parameters.
    Table 6.   5G Polar Parameters
    Parameter Name Values Description
    Mode

    Encoder

    Decoder

    Uplink Decoder with Bit Allocation

    Downlink Encoder with Bit Allocation

    		 Select between encoder, decoder, uplink decoder with bit allocation, or downlink encoder with bit allocation.
    NUM_LIST

    4

    8

    		 List size of the polar list decoder.
    Figure 3.  5G Polar Parameter Editor
  6. For an optional design example, click Generate Example Design
    The software creates a design example.
    Figure 4. Design Example Directory Structure
  7. Click Generate HDL.
Intel® Quartus® Prime generates the RTL and the files necessary to instantiate the IP in your design and synthesize it.
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