5G Polar Intel® FPGA IP User Guide

Download PDF
ID 683766
Date 3/31/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the 5G Polar Intel® FPGA IP 2. Getting Started with the 5G Polar Intel® FPGA IP 3. Designing with the 5G Polar Intel® FPGA IP 4. 5G Polar Intel® FPGA IP Functional Description 5. 5G Polar IP User Guide Archive 6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide
1. About the 5G Polar Intel® FPGA IP x
1.1. 5G Polar Intel® FPGA IP Features 1.2. 5G Polar Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G Polar Intel® FPGA IP 1.4. 5G Polar IP Performance and Resource Utilization
2. Getting Started with the 5G Polar Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G Polar IP Timeout Behavior
3. Designing with the 5G Polar Intel® FPGA IP x
3.1. 5G Polar IP Directory Structure 3.2. Generating a 5G Polar IP 3.3. Simulating the 5G Polar IP with RTL Simulators 3.4. Simulating the 5G Polar IP with MATLAB 3.5. Simulating the 5G Polar IP with the C-model
3.3. Simulating the 5G Polar IP with RTL Simulators x
3.3.1. Simulation Results for the 5G Polar IP
4. 5G Polar Intel® FPGA IP Functional Description x
4.1. 5G Polar IP Signals 4.2. 5G Polar IP Throughput and Latency
1. About the 5G Polar Intel® FPGA IP
2. Getting Started with the 5G Polar Intel® FPGA IP
3. Designing with the 5G Polar Intel® FPGA IP
4. 5G Polar Intel® FPGA IP Functional Description
5. 5G Polar IP User Guide Archive
6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide

4.2. 5G Polar IP Throughput and Latency

Throughput and latency can vary for different input frames, different input LLR values, different locations of frozen bits and parity check bits, and the number of frozen bits that determines code rate. The latency improves by about 5% when you turn off CRC and interleaving, but the throughput remains the same. The NUM_LIST = 8 decoder has approximately 10% longer latency and lower throughput compared to the NUM_LIST = 4 decoder.
Figure 24. Encoder latency and throughputClock frequency = 370MHz. CRC and interleaving off.
Figure 25. Encoder latency and throughputCRC = 6 and interleaving on

For the decoder figures, Rc is the code rate, which equals to number_of_information_bits (K) / code_block_length (N).

Figure 26. Decoder latencyClock frequency = 370MHz. NUM_LIST = 4
Figure 27. Decoder throughput (codeword bit)Clock frequency = 370MHz. NUM_LIST = 4
Figure 28. Decoder throughput (information bit)Clock frequency = 370MHz. NUM_LIST = 4
Level Two Title