5G Polar Intel® FPGA IP User Guide

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ID 683766
Date 3/31/2023
Public

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Document Table of Contents
Document Table of Contents x
1. About the 5G Polar Intel® FPGA IP 2. Getting Started with the 5G Polar Intel® FPGA IP 3. Designing with the 5G Polar Intel® FPGA IP 4. 5G Polar Intel® FPGA IP Functional Description 5. 5G Polar IP User Guide Archive 6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide
1. About the 5G Polar Intel® FPGA IP x
1.1. 5G Polar Intel® FPGA IP Features 1.2. 5G Polar Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G Polar Intel® FPGA IP 1.4. 5G Polar IP Performance and Resource Utilization
2. Getting Started with the 5G Polar Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G Polar IP Timeout Behavior
3. Designing with the 5G Polar Intel® FPGA IP x
3.1. 5G Polar IP Directory Structure 3.2. Generating a 5G Polar IP 3.3. Simulating the 5G Polar IP with RTL Simulators 3.4. Simulating the 5G Polar IP with MATLAB 3.5. Simulating the 5G Polar IP with the C-model
3.3. Simulating the 5G Polar IP with RTL Simulators x
3.3.1. Simulation Results for the 5G Polar IP
4. 5G Polar Intel® FPGA IP Functional Description x
4.1. 5G Polar IP Signals 4.2. 5G Polar IP Throughput and Latency
1. About the 5G Polar Intel® FPGA IP
2. Getting Started with the 5G Polar Intel® FPGA IP
3. Designing with the 5G Polar Intel® FPGA IP
4. 5G Polar Intel® FPGA IP Functional Description
5. 5G Polar IP User Guide Archive
6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide

1.1. 5G Polar Intel® FPGA IP Features

  • Complies with the 3GPP 5G Polar specification
  • Run-time configurable code block length, code rate, frozen bit, and parity check bit locations with optional reconfiguration for each code block
  • Code block length from 32, 64, 128, 256, 512 and 1024
  • Optional built-in bit allocation with uplink Polar decoder or downlink Polar encoder
  • Optional CRC, including CRC6, 11, 16, 24a, 24b and 24c
  • Optional DCI format with RNTI scrambling for CRC24c
  • Optional interleaving and deinterleaving
  • Successive cancellation list decoding scheme, compile-time configurable list size, from L=4 or L=8
  • Decoder output buffering allows the downstream to receive result while the decoder processes the next data block
  • C and MATLAB bit-accurate models for performance simulation and RTL test vector generation
  • System Verilog HDL testbench
  • Avalon® streaming input and output interfaces
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