5G Polar Intel® FPGA IP User Guide

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ID 683766
Date 3/31/2023
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Document Table of Contents
Document Table of Contents x
1. About the 5G Polar Intel® FPGA IP 2. Getting Started with the 5G Polar Intel® FPGA IP 3. Designing with the 5G Polar Intel® FPGA IP 4. 5G Polar Intel® FPGA IP Functional Description 5. 5G Polar IP User Guide Archive 6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide
1. About the 5G Polar Intel® FPGA IP x
1.1. 5G Polar Intel® FPGA IP Features 1.2. 5G Polar Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G Polar Intel® FPGA IP 1.4. 5G Polar IP Performance and Resource Utilization
2. Getting Started with the 5G Polar Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G Polar IP Timeout Behavior
3. Designing with the 5G Polar Intel® FPGA IP x
3.1. 5G Polar IP Directory Structure 3.2. Generating a 5G Polar IP 3.3. Simulating the 5G Polar IP with RTL Simulators 3.4. Simulating the 5G Polar IP with MATLAB 3.5. Simulating the 5G Polar IP with the C-model
3.3. Simulating the 5G Polar IP with RTL Simulators x
3.3.1. Simulation Results for the 5G Polar IP
4. 5G Polar Intel® FPGA IP Functional Description x
4.1. 5G Polar IP Signals 4.2. 5G Polar IP Throughput and Latency
1. About the 5G Polar Intel® FPGA IP
2. Getting Started with the 5G Polar Intel® FPGA IP
3. Designing with the 5G Polar Intel® FPGA IP
4. 5G Polar Intel® FPGA IP Functional Description
5. 5G Polar IP User Guide Archive
6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide

1.4. 5G Polar IP Performance and Resource Utilization

Table 3.  Performance and Resource Usage for Intel® Agilex™ 7 Devices
  • E1V= AGFB014R24B1E1V
  • E2V= AGFB014R24B2E2V
  • E3V= AGFB014R24B2E3V
  • E3E= AGFB014R24B2E3E
  • E4X= AGFB014R24B2E4X
  • E4F= AGFB014R24B2E4F
  • I1V= AGFB014R24B1I1V
  • I2V= AGFB014R24B2I2V
  • I3V= AGFB014R24B2I3V
  • I3E= AGFB014R24B2I3E
Component NUM_LIST ALM M20K DSP fMAX
E1V E2V E3V E3E E4X E4F I1V I2V I3V I3E
Encoder - 2.2k 2 0 848 748 667 1 6671 536 470 848 750 6671 6671
Encoder with bit allocation - 2.3k 3 0 861 776 6671 6671 547 473 870 776 6671 6671
Decoder 4 7.5k 33 0 600 2 500 3 420 4 4204 360 5 3605 6002 5003 4204 4204
Decoder 8 23.2k 56 0 6002 5003 4204 4204 3605 3605 6002 5003 4204 4204
Decoder with bit allocation 4 8.9k 26 0 6002 5003 4204 4204 3605 3605 6002 5003 4204 4204
Decoder with bit allocation 8 24.0k 49 0 6002 5003² 4204 4204 3605 3605 6002 5003 4204 4204
Table 4.  Performance and Resource Usage for Intel Stratix 10 Devices
Component NUM_LIST ALM M20K DSP fMAX
1SG280HU2F50E2VG 1SG280HU2F50E2LG
Encoder - 2.2k 2 0 481 444
Encoder with bit allocation - 2.3k 3 0 497 455
Decoder 4 7.5k 33 0 452 427
Decoder 8 23.2k 56 0 442 413
Decoder with bit allocation 4 8.9k 26 0 454 417
Decoder with bit allocation 8 24.0k 49 0 428 400
1 The maxmium clock speed of M20k blocks operating in simple dual-port RAM mode restrict fMAX to 667 MHz for 3V and -3E devices.
2 The maxmium clock speed of M20k blocks operating in true dual-port RAM mode restricts fMAX to 600MHz for -1V devices.
3

The maxmium clock speed of M20k blocks operating in true dual-port RAM mode restricts fMAX to 500MHz for -2V devices.

4 The maxmium clock speed of M20k blocks operating in true dual-port RAM mode restricts fMAX to 420MHz for -3V and-3E devices.
5 The maxmium clock speed of M20k blocks operating in true dual-port RAM mode restricts fMAX to 360MHz for -4F and -4X devices.
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