5G Polar Intel® FPGA IP User Guide

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ID 683766
Date 3/31/2023
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Document Table of Contents
Document Table of Contents x
1. About the 5G Polar Intel® FPGA IP 2. Getting Started with the 5G Polar Intel® FPGA IP 3. Designing with the 5G Polar Intel® FPGA IP 4. 5G Polar Intel® FPGA IP Functional Description 5. 5G Polar IP User Guide Archive 6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide
1. About the 5G Polar Intel® FPGA IP x
1.1. 5G Polar Intel® FPGA IP Features 1.2. 5G Polar Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G Polar Intel® FPGA IP 1.4. 5G Polar IP Performance and Resource Utilization
2. Getting Started with the 5G Polar Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G Polar IP Timeout Behavior
3. Designing with the 5G Polar Intel® FPGA IP x
3.1. 5G Polar IP Directory Structure 3.2. Generating a 5G Polar IP 3.3. Simulating the 5G Polar IP with RTL Simulators 3.4. Simulating the 5G Polar IP with MATLAB 3.5. Simulating the 5G Polar IP with the C-model
3.3. Simulating the 5G Polar IP with RTL Simulators x
3.3.1. Simulation Results for the 5G Polar IP
4. 5G Polar Intel® FPGA IP Functional Description x
4.1. 5G Polar IP Signals 4.2. 5G Polar IP Throughput and Latency
1. About the 5G Polar Intel® FPGA IP
2. Getting Started with the 5G Polar Intel® FPGA IP
3. Designing with the 5G Polar Intel® FPGA IP
4. 5G Polar Intel® FPGA IP Functional Description
5. 5G Polar IP User Guide Archive
6. Document Revision History for the 5G Polar Intel® FPGA IP User Guide

1. About the 5G Polar Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 23.1
IP Version 2.0.0
The IP implements polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design. Polar codes support the high throughput for 5G new radio (NR).

The IP comprises:

  • Polar encoder and polar list decoder with a list size of 4 or 8
  • Interleaver and deinterleaver
  • CRC encoder and decoder
  • Bit allocator

Polar codes represent a new emerging class of error-correcting codes with power to approach the capacity of a discrete memoryless channel based on the recent invention by Arikan. This new code family is based on a channel polarization concept transforming independent channels into synthesized or polarized channels with different reliabilities: the good and the bad channels. The IP recursively applies such polarization transformation over the resulting channels such that the channels are polarized. The polarized channel encoder transmits information bits (i.e., free bits) over the noiseless channels while assigning fixed bits (i.e., frozen bits) to the noisy ones.


Section Content
5G Polar Intel FPGA IP Features
5G Polar Intel FPGA IP Device Family Support
Release Information for the 5G Polar Intel FPGA IP
5G Polar IP Performance and Resource Utilization

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