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1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Guidelines: I/O PLL Reconfiguration
3.6. Clocking Constraints
3.7. IP Core Constraints
3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core
6.3. IOPLL Reconfig IP Core Reconfiguration Modes
6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
6.5. Address Bus and Data Bus Settings
6.6. Design Example
Visible to Intel only — GUID: zus1564730971374
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6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration
Register Name | Address (Binary) | Counter Bit Setting | |
---|---|---|---|
M Counter | High Count | 00000100 |
|
Low Count | 00000111 | ||
Bypass Enable 15 | 00000101 |
|
|
Odd Division 15 | 00000110 |
|
|
N Counter | High Count | 00000000 |
|
Low Count | 00000010 | ||
Bypass Enable 15 | 00000001 |
|
|
Odd Division 15 | 00000001 |
|
|
C1 Counter | High Count | 00011111 |
|
Low Count | 00100010 | ||
Bypass Enable 15 | 00100000 |
|
|
Odd Division 15 | 00100001 |
|
|
C2 Counter | High Count | 00100011 |
|
Low Count | 00100110 | ||
Bypass Enable 15 | 00100100 |
|
|
Odd Division 15 | 00100101 |
|
|
C3 Counter | High Count | 00100111 |
|
Low Count | 00101010 | ||
Bypass Enable 15 | 00101000 |
|
|
Odd Division 15 | 00101001 |
|
|
C4 Counter | High Count | 00101011 |
|
Low Count | 00101110 | ||
Bypass Enable 15 | 00101100 |
|
|
Odd Division 15 | 00101101 |
|
|
C5 Counter | High Count | 00101111 |
|
Low Count | 00110010 | ||
Bypass Enable 15 | 00110000 |
|
|
Odd Division 15 | 00110001 |
|
|
C6 Counter | High Count | 00110011 |
|
Low Count | 00110110 | ||
Bypass Enable 15 | 00110100 |
|
|
Odd Division 15 | 00110101 |
|
|
C7 Counter | High Count | 00110111 |
|
Low Count | 00111010 | ||
Bypass Enable 15 | 00111000 |
|
|
Odd Division 15 | 00111001 |
|
|
Charge Pump Current 15 | Charge pump setting [2:0] | 00000001 |
|
Charge pump setting [5:3] | 00001101 |
|
|
Bandwidth Setting 15 | — | 00001010 |
|
Ripplecap Setting 15 | — | 00001010 |
|
Calibration 15 | Calibration Request | 01001001 |
|
Calibration Enable | 01001010 |
|
Section Content
Data Bus Setting for Bandwidth Control and Charge Pump
Data Bus Setting for Ripplecap
15 Perform a read-modify-write operation to configure this setting. PLL may lose lock and can cause reliability issue to your device if you configure with the wrong PLL setting, configure the wrong bit, or overwrite the whole byte for settings that made up just part of one byte.