Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

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ID 683761
Date 8/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview 2. F-Series and I-Series Clocking and PLL Architecture and Features 3. F-Series and I-Series Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. IOPLL Reconfig Intel® FPGA IP Core 7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives 8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series
1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration
3. F-Series and I-Series Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Guidelines: I/O PLL Reconfiguration 3.6. Clocking Constraints 3.7. IP Core Constraints 3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
4. Clock Control Intel® FPGA IP Core x
4.1. Release Information for Clock Control Intel® FPGA IP 4.2. Clock Control Intel® FPGA IP Core Parameters 4.3. Clock Control Intel® FPGA IP Core Ports and Signals
5. IOPLL Intel® FPGA IP Core x
5.1. Release Information for IOPLL Intel® FPGA IP 5.2. .mif File Generation 5.3. IP-XACT File Generation 5.4. IOPLL IP Core Parameters 5.5. IOPLL IP Core Ports and Signals
5.2. .mif File Generation x
5.2.1. Generating a New .mif File 5.2.2. Adding Configurations to Existing .mif File
5.3. IP-XACT File Generation x
5.3.1. Generating a New IP-XACT File
5.4. IOPLL IP Core Parameters x
5.4.1. IOPLL IP Core Parameters - PLL Tab 5.4.2. IOPLL IP Core Parameters - Settings Tab 5.4.3. IOPLL IP Core Parameters - Cascading Tab 5.4.4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab 5.4.5. IOPLL IP Core Parameters - Advanced Parameters Tab
6. IOPLL Reconfig Intel® FPGA IP Core x
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP 6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 6.3. IOPLL Reconfig IP Core Reconfiguration Modes 6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core 6.5. Address Bus and Data Bus Settings 6.6. Design Example
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core x
6.2.1. Connectivity between the IOPLL and IOPLL Reconfig IP Cores 6.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores
6.3. IOPLL Reconfig IP Core Reconfiguration Modes x
6.3.1. .mif Streaming Reconfiguration 6.3.2. Advanced Mode Reconfiguration 6.3.3. Clock Gating Reconfiguration 6.3.4. Dynamic Phase Shift Reconfiguration
6.3.1. .mif Streaming Reconfiguration x
6.3.1.1. Recalibration Using .mif
6.3.2. Advanced Mode Reconfiguration x
6.3.2.1. Recalibration Using Advanced Mode
6.5. Address Bus and Data Bus Settings x
6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration 6.5.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration 6.5.3. Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core
6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration x
6.5.1.1. Data Bus Setting for Bandwidth Control and Charge Pump 6.5.1.2. Data Bus Setting for Ripplecap
6.6. Design Example x
6.6.1. Reconfiguration Option: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core 6.6.2. Reconfiguration Option: Advanced Mode Reconfiguration and Recalibration Using IOPLL Reconfig IP Core 6.6.3. Reconfiguration Option: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series

Document Version Quartus® Prime Version Changes
2024.08.21 24.1 Updated the Data Bus Bit Setting (Binary) value in Table: Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration.
2024.07.26 24.1
  • Added a note for Figure: I/O-PLL-to-I/O-PLL Cascading Via Dedicated Cascade Path.
  • Corrected the description for extswitch from high to low for the Switchover Mode parameter.
  • Added a footnote to the Figure: Connectivity between the IOPLL and IOPLL Reconfig IP Cores in the Quartus Prime Software.
2024.04.01 24.1 Added new parameter Ensure glitch free clock switchover in Table: Clock Control Intel® FPGA IP Core Parameters for F-Series and I-Series Devices.
2023.07.13 23.1 Corrected typographical errors.
2023.04.10 23.1
  • Updated product family name to "Intel Agilex® 7".
  • Retitled the document from Intel® Agilex™ Clocking and PLL User Guide to Intel Agilex® 7 Clocking and PLL User Guide: F-Series and I-Series.
  • Updated footnotes in PLL Features in M-Series Devices—Preliminary table in PLL Features section.
  • Updated IOPLL IP Core Ports for F-Series and I-Series Devices table in IOPLL IP Core Ports and Signals section.
  • Added Related Information in PLL Locations section.
  • Updated IOPLL Intel® FPGA IP Core Current Release Information table in IOPLL Intel® FPGA IP Core section.
2022.11.09 20.3 Updated User Calibration with additional information and related information.
2022.03.26 20.3 Updated the gated and ungated data bus bit setting (binary) in the Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration table.
2021.12.13 20.3 Updated the connection for the dedicated clock inputs in the Fabric-Feeding I/O PLL High-Level Block Diagram for Intel Agilex Devices diagram.
2021.09.21 20.3
  • Updated the description in the Root Clock Gate section.
  • Added a note in the PLL Architecture section.
  • Added description on PLL loses lock in the Locked section.
  • Updated the Manual Switchover mode description for the Switchover Mode parameter in the IOPLL IP Core Parameters - Settings Tab for Intel Agilex Devices table.
  • Updated the address for C1 to C7 counters in the Address Bus and Data Bus Settings for Advanced Mode Reconfiguration table.
  • Updated data[7:4] for C1 to C7 counters in the Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core table.
  • Updated mgmt_writedata[7..0] signal in the Waveform Example for Advanced Mode Reconfiguration Design Example diagram.
  • Updated mgmt_writedata[7..0] signal in the Waveform Example for Clock Gating Reconfiguration Design Example diagram.
2021.06.21 20.3 Updated the PLL Locations section.
2021.03.29 20.3
  • Added table: Spread-Spectrum Input Clocking Supported Profile.
  • Added guideline: Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP .
  • Updated the IOPLL Reconfig Intel® FPGA IP Core Current Release Information table.
2020.09.28 20.3
  • Updated the note to the spread-spectrum input clock tracking feature in the PLL Features in Intel Agilex Devices table.
  • Added the IP-XACT File Generation section under IOPLL Intel® FPGA IP Core.
  • Updated the Charge Pump Setting [2:0] value for Multiple Factor 141–160 in the Fabric-Feeding I/O PLL Data Bus Setting for Bandwidth Control and Charge Pump (For High Bandwidth) table.
  • Updated the high bandwidth ripplecap setting for Multiply Factor 141–160 in the Fabric-Feeding I/O PLL Data Bus Setting for Ripplecap table.
  • Updated C counters in the following sections:
    • I/O Bank I/O PLL High-Level Block Diagram for Intel Agilex Devices
    • Fabric-Feeding I/O PLL High-Level Block Diagram for Intel Agilex Devices
    • Address Bus and Data Bus Settings for Advanced Mode Reconfiguration table
    • Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration table
    • Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core table
2020.04.13 20.1
  • Updated the Examples of Clock Networks Sizes Using Intel Agilex Programmable Clock Routing diagram.
  • Removed zero-delay buffer compensation support for fabric-feeding I/O PLL in the following sections:
    • PLL Features in Intel Agilex Devices table
    • Fabric-Feeding I/O PLL High-Level Block Diagram for Intel Agilex Devices diagram
  • Added description for top and bottom sub-banks in the PLL Locations section. Updated the I/O PLL Locations in I/O Bank diagram.
  • Updated the Zero-Delay Buffer Mode section.
    • Mentioned that the ZDB mode is only supported for I/O bank I/O PLL.
    • Added description about the bidirectional I/O pin must not be globally promoted.
  • Added information on IOPLL Reconfig IP ports in the PLL Reconfiguration and Dynamic Phase Shift section. Moved the information from the IOPLL Reconfig Intel® FPGA IP Core section.
  • Added a note to zero delay buffer for Compensation Mode in the IOPLL IP Core Parameters - PLL Tab for Intel Agilex Devices table.
  • Added description on supported output clocks and C counters in the IOPLL IP Core Parameters - Advanced Parameters Tab for Intel Agilex Devices table.
  • Added a design example with three reconfiguration options using IOPLL Reconfig Intel® FPGA IP core.
2019.12.18 19.3 Removed scanclk signal in the Guideline: I/O PLL Reconfiguration section.
2019.10.31 19.3
  • Added the Examples of Clock Networks Sizes Using Intel Agilex Programmable Clock Routing diagram in the Programmable Clock Routing section.
  • Updated the number of resources available in the Programmable Clock Routing Resources for Intel Agilex Devices table.
  • Updated the PLL Features in Intel Agilex Devices table.
    • Updated C counter divide factor range from '1 to 510' to '1 to 512'.
    • Added a note to dedicated external clock outputs.
    • Removed the following PLL features for fabric-feeding I/O PLL.
      • Dedicated external clock outputs
      • External feedback input pin
      • External feedback compensation
    • Added spread-spectrum input clock tracking feature.
  • Updated the PLL Usage section.
  • Removed external feedback mode in the Fabric-Feeding I/O PLL High-Level Block Diagram for Intel Agilex Devices diagram.
  • Clarified that EFB mode is only supported for I/O bank I/O PLL.
  • Updated the PLL Cascading section.
    • Added description that Intel Agilex devices does not support I/O PLL cascading within the same I/O bank.
    • Updated outclk[8:0] to outclk[6:0] in the I/O-PLL-to-I/O-PLL cascading diagrams.
  • Added the following guidelines:
    • Guideline: I/O PLL Reconfiguration
    • Clocking Constraints
    • IP Core Constraints
  • Added information for the following IP cores:
    • Clock Control Intel® FPGA IP version 1.0.0
    • IOPLL Intel® FPGA IP version 19.3.0
    • IOPLL Reconfig Intel® FPGA IP version 19.3.0
2019.04.02 — Initial release.
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