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1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Guidelines: I/O PLL Reconfiguration
3.6. Clocking Constraints
3.7. IP Core Constraints
3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core
6.3. IOPLL Reconfig IP Core Reconfiguration Modes
6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
6.5. Address Bus and Data Bus Settings
6.6. Design Example
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6.5.1.2. Data Bus Setting for Ripplecap
Multiply Factor 17 | Ripplecap Setting Address = 00001010 Data [2:1] |
||
---|---|---|---|
Low Bandwidth | Medium Bandwidth | High Bandwidth | |
4–5 | 2'b01 | 2'b01 | 2'b00 |
6–7 | 2'b11 | 2'b01 | 2'b01 |
8–10 | 2'b11 | 2'b01 | 2'b01 |
11–15 | 2'b11 | 2'b01 | 2'b01 |
16–20 | 2'b11 | 2'b01 | 2'b01 |
21–23 | 2'b11 | 2'b01 | 2'b01 |
24–43 | 2'b11 | 2'b01 | 2'b01 |
44–64 | 2'b11 | 2'b01 | 2'b01 |
65–85 | 2'b11 | 2'b01 | 2'b01 |
86–124 | 2'b11 | 2'b01 | 2'b01 |
125–160 | 2'b11 | 2'b01 | 2'b01 |
Multiply Factor 17 | Ripplecap Setting Address = 00001010 Data [2:1] |
|
---|---|---|
Medium Bandwidth | High Bandwidth | |
4–5 | 2'b01 | 2'b00 |
6–7 | 2'b01 | 2'b00 |
8–10 | 2'b01 | 2'b01 |
11–15 | 2'b01 | 2'b01 |
16–20 | 2'b01 | 2'b01 |
21–23 | 2'b01 | 2'b01 |
24–43 | 2'b01 | 2'b01 |
44–64 | 2'b01 | 2'b01 |
65–85 | 2'b01 | 2'b01 |
86–104 | 2'b01 | 2'b01 |
105–140 | 2'b01 | 2'b01 |
141–160 | 2'b01 | 2'b01 |
17 If you select the Use Nondedicated Feedback Path option under the Normal or Source Synchronous compensation mode, the Multiply Factor is M x C i , where M is M counter value while C i is the Compensated Outclk C counter value. Else, the Multiply Factor is only the M counter value.