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1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Guidelines: I/O PLL Reconfiguration
3.6. Clocking Constraints
3.7. IP Core Constraints
3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core
6.3. IOPLL Reconfig IP Core Reconfiguration Modes
6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
6.5. Address Bus and Data Bus Settings
6.6. Design Example
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6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
Port | Direction | Description |
---|---|---|
mgmt_clk | Input | Dynamic reconfiguration clock that drives the IOPLL Reconfig IP core. The maximum input clock frequency is 100 MHz. This clock can be an independent clock source. It must be free running, which means it cannot be connected to the output of the I/O PLL being reconfigured. |
mgmt_reset | Input | Active high signal. Synchronous reset input to clear all the data in the IOPLL Reconfig IP core. |
mgmt_waitrequest | Output | This port goes high when PLL reconfiguration process started and remains high during PLL reconfiguration. After PLL reconfiguration process completed, this port goes low. |
mgmt_write | Input | Active high signal. Asserts to indicate a write operation. |
mgmt_read | Input | Active high signal. Asserts to indicate a read operation. |
mgmt_writedata[7..0] | Input | Writes data to this port when mgmt_write signal is asserted. |
mgmt_readdata[7..0] | Output | Reads data from this port when mgmt_read signal is asserted. |
mgmt_address[9..0] | Input | Specifies the address of the data bus for a read or write operation. |
reconfig_from_pll[10..0] | Input | Bus that connects to reconfig_from_pll[10..0] bus in the IOPLL Intel® FPGA IP core. |
reconfig_to_pll[29..0] | Output | Bus that connects to reconfig_to_pll[29..0] bus in the IOPLL IP core. |