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1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Guidelines: I/O PLL Reconfiguration
3.6. Clocking Constraints
3.7. IP Core Constraints
3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core
6.3. IOPLL Reconfig IP Core Reconfiguration Modes
6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
6.5. Address Bus and Data Bus Settings
6.6. Design Example
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6.6.2. Reconfiguration Option: Advanced Mode Reconfiguration and Recalibration Using IOPLL Reconfig IP Core
After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration at medium bandwidth:
- 400 MHz with 0 ps phase shift on counter C1 output
- 200 MHz with 0 ps phase shift on counter C2 output
The state machine initiates the I/O PLL recalibration process when the I/O PLL reconfiguration operation is complete.
To run the design example using advanced mode reconfiguration, perform these steps:
- Open AN.stp file and program the device top.sof.
- In the In-System Sources & Probes IP core, assert mode_0 to high pulse and mode_1 remains low.
- Assert a high pulse on the mgmt_reset signal to reset the IOPLL Reconfig IP core.
- Assert a high pulse on the reset_SM signal to start the I/O PLL reconfiguration operation.
Figure 26. Waveform Example for Advanced Mode Reconfiguration Design Example