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1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Guidelines: I/O PLL Reconfiguration
3.6. Clocking Constraints
3.7. IP Core Constraints
3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core
6.3. IOPLL Reconfig IP Core Reconfiguration Modes
6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
6.5. Address Bus and Data Bus Settings
6.6. Design Example
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2.2.1. PLL Features
Feature | I/O Bank I/O PLL | Fabric-Feeding I/O PLL |
---|---|---|
Integer PLL | Yes | Yes |
Number of C output counter | 7 | 3 |
M counter divide factor range | 4 to 160 | 4 to 160 |
N counter divide factor range | 1 to 110 | 1 to 110 |
C counter divide factor range | 1 to 512 | 1 to 512 |
Dedicated external clock outputs 2 | Yes | — |
Dedicated clock input pins3 | Yes | Yes |
External feedback input pin | Yes | — |
Source synchronous compensation 4 | Yes | Yes |
Direct compensation | Yes | Yes |
Normal compensation 4 | Yes | Yes |
Zero-delay buffer compensation | Yes | — |
External feedback compensation | Yes | — |
LVDS compensation | Yes | — |
Voltage-controlled oscillator (VCO) output drives the DPA clock | Yes | — |
Phase shift resolution 5 | 78.125 ps | 78.125 ps |
Programmable duty cycle | Yes | Yes |
Power down mode | Yes | Yes |
Bandwidth setting | Low, medium, and high | Medium and high |
Spread-spectrum input clock tracking 6 | Yes | Yes |
Spread-Spectrum Clocking Parameter | Setting |
---|---|
Modulation frequency | 200 kHz |
Center or down spread | Down spread |
Frequency deviation | ±1% |
Modulation profile | Triangle |
2 For dedicated external clock outputs, you must enable access to external clock output port through IOPLL Intel® FPGA IP core. There are 2 dedicated external clock output available for each I/O bank I/O PLL.
3 I/O PLL only supports True Differential Signaling for dedicated clock input pins.
4 Non-dedicated feedback path option is available for this compensation mode.
5 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the F-Series and I-Series devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
6 Provided that input clock jitter is within the input jitter tolerance specifications. Intel recommends that the spread-spectrum support profile is down spread, ±0.5% and Fmod = 200 kHz.