AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.3.1.1.2. Nios® II Subsystem in Platform Designer

The Nios® II subsystem Platform Designer project, nios_subsystem.qsys, instantiates the following peripherals:

  • Nios® II processor
  • On-chip memory (altera_avalon_onchip_memory2)—provides both instruction and data memory space
  • Timer—provides a general timer function for the software
  • JTAG UART—serves as the main communications portal between the user and the Nios® II processor via the terminal console in Nios® II SBT for Eclipse tool
  • Avalon® -MM bridges—two Avalon® -MM bridge modules; one to interface to the JESD204B subsystem and the other interface to the Platform Designer components (core PLL reconfiguration controller and SPI master module)
  • PIO—provides general input/output (I/O) access from the Nios® II processor to the HDL components in the FPGA via two sets of 32-bit registers:
    • io_status—status registers input from the HDL components to the Nios® II processor
    • io_control—control registers output from the Nios® II processor to the HDL components
Table 10.   Signal Connectivity for io_status Registers
Bit Signal
0 Core PLL locked
1 TX transceiver ready (Link 0/Instance 0)
2 RX transceiver ready (Link 0/Instance 0)
3 Test pattern checker data error (Link 0/Instance 0)
4–31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signals for subsequent JESD204B IP cores (Link 1-9/ Instance 1-9), if present.
Table 11.   Signal Connectivity for io_control Registers
Bit Signal
0 RX serial loopback enable for two JESD204B IP cores in this design
1 Reserved
2 Reserved
3 Reserved
4–30 Reserved
31 Sysref

You can access the address map of the submodules in the Nios® II subsystem by clicking on the Address Map tab in the Platform Designer window.


Section Content
Nios II Processor
Nios II Subsystem Address Map

Level Two Title