AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.2.4.1. Functions in main.c Source File

Most of the function prototypes of the sub functions listed in the following table can be found in the functions.h or main.c header file located in the software folder.

Table 4.  Functions in main.c Source File
Function Prototype Description
int StringIsNumeric (char *) Tests whether the string is numeric. Returns 1 if true, 0 if false.
void DelayCounter(alt_u32 count) Delay counter. Counts up to count ticks, each tick is approximately 1 second.
int Initialize(char *options[ ] [MAX_OPTIONS_CHAR], int *held_resets) Performs the link initialization by executing Test, Sysref, and DelayCounter functions. Return1 if fail.
int Status(char *options[][MAX_OPTIONS_CHAR]) Executes the report link status command according to the options.
int Loopback (char* options [ ][MAX_OPTIONS_CHAR ], int *held_resets, int dnr) Executes the loopback command according to the options. Returns 0 if success, 1 if fail.
int SourceDest (char *options[][MAX_OPTIONS_CHAR], int *held_resets, int dnr) Executes source or destination datapath selection command according to the options. Return 0 if success, 1 if fail.
int Test(char *options[][MAX_OPTIONS_CHAR], int *held_resets)

Executes test mode command according to the options. Test mode:

  • Set source/destination datapath selection to PRBS/RAMP/ALT test pattern generator/checker.
  • Set transceiver to internal/external serial loopback.

Return 0 if success, 1 if fail.
void Sysref (void) Pulse SYSREF one time
int ResetSeq(int link, int *held Performs full hardware reset sequence through the software interface on the indicated link. Returns 0 if success, 1 if fail.
int ResetForce(int link, int reset_val, int hr, int *held_resets) Forces reset assertion or deassertion on submodule resets indicated by reset_val for the indicated link. The function also decides whether assert and hold, deassert, or pulse the indicated resets. Returns 0 if success, 1 if fail.
int Reset_X_L_F_Release(int link, int instances, int *held_resets) Deasserts the transceiver, link, and frame resets. The function deasserts the TX transceiver reset first, after the TX transceiver ready signal asserts, it clears the TX error status register. Next, deasserts the TX link and TX frame resets. The function repeats the above actions for the RX side. Return 0 if success, 1 if fail.
void InitISR(void)

Initializes the interrupt controllers for the following peripherals:

  • JESD204B IP core TX CSR
  • JESD204B IP core RX CSR
  • SPI Master

The timer and JTAG UART interrupt controllers are disabled. Modify the function to suit your design.

void ProgCSR(void) Programs the JESD204B IP core CSR (e.g. program RBD offset)
static void ISR_JESD_RX(void * context) JESD204B IP core RX ISR. Upon an interrupt event (IRQ asserted), the function reads the RX JESD204B CSR rx_err0 and rx_err1 registers and reports the error code. Consequently, the ISR clears all valid and active status registers in the rx_err0 and rx_err1 registers.
static void ISR_JESD_TX(void * context)

JESD204B IP core TX ISR. Upon an interrupt event (IRQ asserted), the function reads the TX JESD204B CSR tx_err registers and reports the error code. Consequently, the ISR clears all the valid and active status registers in the tx_err registers.

static void ISR_SPI(void * context) The SPI master ISR. Upon an interrupt event (IRQ assert), it clears the IRQ flag and return.
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