AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.2.4.2. Custom Peripheral Access Macros in macros.c Source File

You can use the peripheral access macros to access specific information in CSR of the following peripherals:
  • Reset sequencer
  • JESD204B TX
  • JESD204B RX
  • PIO control
  • PIO status
  • Transceiver PHY Reset Controller
  • fPLL
  • Core PLL Reconfiguration
Table 5.  Custom Peripheral Access Macros in macros.cMost of the function prototypes below can be found in the macros.h header file located in the software folder.
Function Prototype Description
int CALC_BASE_ADDRESS_LINK (int base, int link) Calculates and returns the base address based on the link provided. Note the link needs to be 0 because there is only one reset sequencer in the JESD204B subsystem. Hence, set the MAX_LINKS parameter in the main.h header file to 1. You are responsible to set the parameter correctly to reflect the system configuration.
int CALC_BASE_ADDRESS_XCVR_NATIVE (int base, int instance) Calculate and returns the base address of transceiver reconfiguration based on the instance number of JESD204B IP core. The number of transceiver per JESD204B subsystem in the design is defined by MAX_INSTANCES parameter in the main.h header file. This function is not used due to the design doesn’t perform data rate reconfiguration.
int IORD_RESET_SEQUENCER_STATUS_REG (int link) Read reset sequencer status register at link and return the value.
int IORD_RESET_SEQUENCER_RESET_ACTIVE (int link) Read reset sequencer status register at link and return 1 if the reset active signal is asserted, else return 0.
void IOWR_RESET_SEQUENCER_INIT_RESET_SEQ (int link) Write reset sequencer at link to trigger full hardware reset sequence.
void IOWR_RESET_SEQUENCER_FORCE_RESET (int link, int val) Write reset sequencer at link to force assert or deassert resets based on the val value.
int IORD_JESD204_TX_STATUS0_REG (int link, int instance) Read the JESD204B TX CSR tx_status0 register at link and instance and return the value.
int IORD_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link, int instance) Read the JESD204B TX CSR syncn_sysref_ctrl register at link and instance and return the value.
void IOWR_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link, int instance, int val) Write val value into the JESD204B TX CSR syncn_sysref_ctrl register at link and instance.
int IORD_JESD204_RX_STATUS0_REG (int link, int instance) Read JESD204B CSR rx_status0 register at link and instance and return value.
int IORD_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link, int instance) Read JESD204B RX CSR syncn_sysref_ctrl register at link and instance and return value.
void IOWR_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link, int instance, int val) Write val value into JESD204B RX CSR syncn_sysref_ctrl register at link and instance.
int IORD_PIO_CONTROL_REG (void) Read the PIO control register and return the value.
void IOWR_PIO_CONTROL_REG (int val) Write val value into the PIO control register.
int IORD_PIO_STATUS_REG (void) Read the PIO status register and return the value.
int IORD_JESD204_TX_TEST_MODE_REG (int link, int instance) Read the JESD204B TX CSR tx_test register at link and instance and return the value.
int IORD_JESD204_RX_TEST_MODE_REG (int link, int instance) Read the JESD204B RX CSR rx_test register at link and instance and return the value.
void IOWR_JESD204_TX_TEST_MODE_REG (int link, int instance, int val) Write val value into the JESD204B TX CSR tx_test register at link and instance.
void IOWR_JESD204_RX_TEST_MODE_REG (int link, int instance, int val) Write val value into the JESD204B RX CSR rx_test register at link and instance.
int IORD_JESD204_RX_ERR0_REG (int link, int instance) Read the JESD204B RX CSR rx_err0 register at link and instance and return the value.
void IOWR_JESD204_RX_ERR0_REG (int link, int instance, int val) Write val value the JESD204B rx_err0 register at link and instance.
int IORD_JESD204_RX_ERR1_REG (int link, int instance) Read the JESD204B RX CSR rx_err1 register at link and instance and return the value.
void IOWR_JESD204_RX_ERR1_REG (int link, int instance, int val) Write val value the JESD204B rx_err1 register at link and instance.
int IORD_JESD204_TX_ERR_REG (int link, int instance) Read the JESD204B TX CSR tx_err register at link and instance and return the value.
void IOWR_JESD204_TX_ERR_REG (int link, int instance, int val) Write val value into the JESD204B TX CSR tx_err register at link an instance.
int IORD_JESD204_TX_ERR_EN_REG (int link, int instance) Read the JESD204B TX CSR tx_err_enable register at link and instance and return the value.
void IOWR_JESD204_TX_ERR_EN_REG (int link, int instance, int val) Write val value into the JESD204B TX CSR tx_err_enable register at link and instance.
int IORD_JESD204_RX_ERR_EN_REG (int link, int instance) Read the JESD204B RX CSR rx_err_enable register at link and instance and return the value.
void IOWR_JESD204_RX_ERR_EN_REG (int link, int instance, int val) Write the JESD204B RX CSR rx_err_enable register at link and instance.
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