1.3.1.1.1. JESD204B Subsystem
The JESD204B subsystem Platform Designer project, jesd204b_subsystem.qsys, instantiates the following modules:
- Two x8-lane JESD204B IP cores configured in duplex, bonded mode (with TX and RX data paths)
- Reset sequencer
- Transceiver PHY reset controller
- fPLL
- Avalon® -MM bridge
JESD204B IP Core
The JESD204B IP base core and PHY layer connect to Nios® II processor via the Avalon® -MM interconnect. There are three separate Avalon® -MM ports for the JESD204B IP core:
- Base core TX data path—For dynamic reconfiguration of TX CSR parameters
- Base core RX data path—For dynamic reconfiguration of RX CSR parameters
- PHY layer—For dynamic reconfiguration of transceiver PHY CSR (including data rate reconfiguration)
| Parameter | Value | Description |
|---|---|---|
| Subclass | 1 | Subclass mode |
| L | 8 | Number of lanes per converter device |
| M | 4 | Number of converters per device |
| F | 1 | Number of octets per frame |
| S | 1 | Number of transmitted samples per converter per frame |
| N | 16 | Number of conversion bits per converter |
| N’ | 16 | Number of transmitted bits per sample |
| K | 32 | Number of frames per multiframe |
| CS | 0 | Number of control bits per conversion sample |
| CF | 0 | Number of control words per frame clock period per link |
| HD | 1 | High Density user data format |
| SCR | On | Enable scrambler |
Reset Sequencer
The reset sequencer generates the system resets for the following modules in the system:
- Core PLL reset—resets the core PLL.
- TX/RX Transceiver PHY reset—resets the TX/RX JESD204B IP cores PHY module.
- TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP cores configuration status registers.
- TX/RX link reset—resets the TX/RX JESD204B IP cores base module, transport layer.
- TX/RX frame reset—resets the TX/RX transport layer, pattern generator and checker modules.
You can issue hardware reset or software reset to the reset sequencer. The reset input pin of the reset sequencer is connected to the PB0 push button on the Intel® Arria® 10 FPGA development kit. Press PB0 push button to generate the hardware reset. The Nios® II software generates the software reset to reset sequencer. The reset sequencer has a pre-defined reset sequence as shown in the following figure. The figure also shows the components that are affected by the reset outputs of the reset sequencer.
The hardware reset follows this predefined sequence. The software reset has the flexibility of following this predefined reset sequence or overwriting the reset sequence.
Figure 10. Reset Sequence
Transceiver PHY Reset Controller
The transceiver PHY reset controller receives the transceiver PHY reset output from the reset sequencer. It generates the proper analog and digital reset sequence for the two x8-lane JESD204B IP cores PHY module.
fPLL
The fPLL is the TX PLL. It generates the fast clock for the serial data in PMA and parallel clock for the parallel data in PMA and PCS. The reference clock input to the fPLL is the device_clk.
Avalon® -MM Bridge
All the Avalon® -MM slaves in the JESD204B subsystem are connected via Avalon® -MM interconnect to a single Avalon® -MM bridge. This bridge is the single interface for Avalon® -MM communications into and out of system.
JESD204B Subsystem Address Map
You can access the address map of slaves in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window. The design contains two JESD204B IP cores instances only per subsystem, so instance 2 and 3 in the following table are excluded.
| Avalon® -MM Peripheral | Address Map |
|---|---|
| JESD204B IP cores transceiver reconfiguration interfaces |
|
| fPLL | 0x0000_8000 - 0x0000_8fff |
| JESD204B IP cores CSR - TX |
|
| JESD204B IP cores CSR - RX |
|
| Reset Sequencer | 0x0000_e000 - 0x0000_e0ff |