AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.3.1.1.2.1. Nios® II Processor

The reference design uses Nios® II processor as a control unit to control certain aspects of JESD204B system using C-based software control flow. The software C codes included as part of this reference design only perform basic JESD204B link initialization. You can modify the C codes based on your system specifications.

Figure 11. Software Main C Code Execution Flow

The JESD204B link initialization performs the following tasks:

  • Set the pattern type or user mode for the pattern generator or checker. The default pattern type is set to PRBS.
  • Set the loopback mode. The default is external serial loopback mode.
  • Pulse SYSREF (required to meet Subclass 1 requirements)
  • Wait 10 seconds to allow for changes to take effect.
  • Report the link status.

The SYSREF signal acts as a common timing reference for multiple JESD204B Subclass 1 devices in a JESD204B system to achieve deterministic latency. In general, SYSREF is a source synchronous to the device clock from single clock chip. In most cases, the register in the IP core, which detects this SYSREF signal, is far away from the SYSREF pin. The long interconnect routing delay may result in timing violation. Because of there is no clock generator on the development kit that can provide SYSREF to JESD204B IP cores, the PIO is used to generate the SYSREF pulse. The Nios® II processor instructs the PIO to generate SYSREF pulse, which is re-timed by two stages pipeline registers before being sampled by each IP core. Refer to the JESD204B IP Core User Guide for constraining SYSREF signal if it is coming from FPGA input pin.

Figure 12. Two Stage Pipeline Registers for SYSREF Signal

The initialized ISR performs the following tasks:

  • Print and clear the RX/TX JESD204B error status registers.
  • Disable timer and JTAG UART interrupt generation.
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