AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

Download PDF
ID 683731
Date 1/30/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA

Perform the following steps to regenerate HDL files, compile, generate programming file, and configure the FPGA:

  1. Download the reference design file to your local project directory.
  2. Launch the Intel® Quartus® Prime software.
  3. On the File menu, click New Project Wizard.
  4. On the New Project Wizard page, open Design Template Installation. Select the design template you want install. Click Next, then Finish.
  5. Note:

    The reference design provided does not enable Signal Tap Logic Analyzer in the Intel® Quartus® Prime project. Remove the following commands in jesd204b_ed.sdc file to avoid warnings if you do not compile the design with the provided Signal Tap file:

    • Intel® Quartus® Prime Standard Edition
      • u_jesd204b_ed_qsys|jesd204b_subsystem_0|jesd204b_duplex0|g_xcvr_native_insts[*]|tx_clkout \
      • u_jesd204b_ed_qsys|jesd204b_subsystem_0|jesd204b_duplex1|g_xcvr_native_insts[*]|tx_clkout \
    • Intel® Quartus® Prime Pro Edition
      • u_jesd204b_ed_qsys|jesd204b_subsystem_0|jesd204b_duplex0|jesd204b_duplex0|g_xcvr_native_insts[*]|tx_clkout \
      • u_jesd204b_ed_qsys|jesd204b_subsystem_0|jesd204b_duplex1|jesd204b_duplex1|g_xcvr_native_insts[*]|tx_clkout \
    To include the Signal Tap file into Intel® Quartus® Prime project, navigate to the Assignments menu and select Settings. Click on the Signal Tap Logic Analyzer under Category, and then check the Enable Signal Tap Logic Analyzer checkbox. Browse the stp1.stp file (located at /stp directory) and hit OK button.
  6. To regenerate HDL files and compile the design with or without Signal Tap file,
    1. Open the Intel® FPGA GPIO parameter editor (se_outbuf_1bit.qsys) and click Generate HDL.
    2. Repeat step a. to generate HDL files for jesd204b_ed_qsys.qsys and dl_count.qsys.
    3. Once the Platform Designer generation are done for all system files, navigate to the Processing menu and select Start Compilation.
  7. Ensure the following:
    1. The Intel® FPGA Download Cable II driver are installed on the host computer.
    2. The board is powered.
    3. No other running application is uses the JTAG chain.
  8. On the Tools menu, click Programmer.
  9. Click Auto Detect to display the devices in the JTAG chain and select a device.
  10. Right click and select Change File. Then, select the appropriate jesd204b_ed.sof file from the <project directory>/output_files and click Open.
  11. Turn on the Program/Configure option for the .sof file.
  12. Click Start to download the .sof file to the FPGA.
Level Two Title