Visible to Intel only — GUID: xls1494998589115
Ixiasoft
1.3.2. Clocking Scheme
The reference design requires two clock sources coming from the Intel® Arria® 10 GX FPGA development kit for proper operation. The reference design uses the default 100Mhz clock frequency from on-board oscillator.
Signal Name | Description | Usage |
---|---|---|
device_clk | External 100 Mhz clock from X3 Si570 Programmable Oscillator. | Input reference clock for core PLL (IO PLL), TX transceiver fPLL, RX transceiver CDR. |
link_clk | Link and transport layer clock from core PLL (IO PLL). | Clock source for each JESD204B IP Core link layer and transport layer link interface, deterministic latency measurement module. |
frame_clk | Transport and application layer clock from core PLL (IO PLL). | Clock source for each transport layer, test pattern generator and checker. |
mgmt_clk | External 100 Mhz clock from X3 Si570 Programmable Oscillator. | Management clock for nios II subsystem, transceiver reconfiguration interfaces, JESD204B IP cores Avalon-MM interfaces, altera PLL reconfig, SPI master, frequency checker. |