AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Public
Document Table of Contents

1.3.2. Clocking Scheme

The reference design requires two clock sources coming from the Intel® Arria® 10 GX FPGA development kit for proper operation. The reference design uses the default 100Mhz clock frequency from on-board oscillator.

Table 13.  Reference Design System Clock Summary
Note: The IOPLL input reference clock is sourcing from device clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network might introduce additional jitter to the IOPLL and transceiver PLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.
Signal Name Description Usage
device_clk External 100 Mhz clock from X3 Si570 Programmable Oscillator. Input reference clock for core PLL (IO PLL), TX transceiver fPLL, RX transceiver CDR.
link_clk Link and transport layer clock from core PLL (IO PLL). Clock source for each JESD204B IP Core link layer and transport layer link interface, deterministic latency measurement module.
frame_clk Transport and application layer clock from core PLL (IO PLL).

Clock source for each transport layer, test pattern generator and checker.

mgmt_clk External 100 Mhz clock from X3 Si570 Programmable Oscillator. Management clock for nios II subsystem, transceiver reconfiguration interfaces, JESD204B IP cores Avalon-MM interfaces, altera PLL reconfig, SPI master, frequency checker.