Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

ID 683686
Date 9/12/2024
Public
Document Table of Contents

1.1. Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet

Arria® 10 FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 2.1 or 3.0. The Arria® 10 Hard IP for PCI Express* with Single Root I/O Virtualization (SR-IOV) IP core consists of this hardened protocol stack and the SR-IOV soft logic. The SR-IOV soft logic uses the Configuration Space Bypass mode of the Hard IP to bypass the internal configuration block and BAR matching logic. These functions are implemented in external soft logic. Soft logic in the SR-IOV Bridge also implements interrupts and error reporting.

The SR-IOV Bridge was redesigned to support up to 8 Physical Functions (PFs) and 2048 Virtual Functions (VFs). The SR-IOV bridge also supports the Address Translation Services (ATS) and TLP Processing Hints (TPH) capabilities.

Figure 1.  Arria® 10 PCIe Variant with SR-IOVThe following figure shows the high-level modules and connecting interfaces for this variant.
Figure 2.  Arria® 10 PCIe Variant with SR-IOVThe following figure provides the next level of detail for the modules that comprise the SR-IOV Bridge.
Table 2.  PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen2 and Gen3 for supported link widths. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga‑transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to about 1.5%.

Link Width
×4 ×8

PCI Express Gen2 (5.0 Gbps) - 256-bit interface

N/A 32

PCI Express Gen3 (8.0 Gbps) - 256-bit interface

31.51 63