Visible to Intel only — GUID: nik1410564902065
Ixiasoft
Visible to Intel only — GUID: nik1410564902065
Ixiasoft
5.17. PIPE Interface Signals
These PIPE signals are available for Gen1, Gen2, and Gen3 variants so that you can simulate using either the serial or the PIPE interface. Note that Arria® 10 and Cyclone® 10 GX devices do not support the Gen3 PIPE interface. Simulation is faster using the PIPE interface because the PIPE simulation bypasses the SERDES model. By default, the PIPE interface is 8 bits for Gen1 and Gen2 and 32 bits for Gen3. You can use the PIPE interface for simulation even though your actual design includes a serial interface to the internal transceivers. However, it is not possible to use the Hard IP PIPE interface in hardware, including probing these signals using Signal Tap Embedded Logic Analyzer. These signals are not top-level signals of the Hard IP. They are listed here to assist in debugging link training issues.
Signal |
Direction |
Description |
---|---|---|
currentcoeff0[17:0] | Output |
For Gen3, indicates the coefficients to be used by the transmitter. The 18 bits specify the following coefficients:
|
currentrxpreset0[2:0] | Output |
For Gen3 designs, specifies the current preset. |
eidleinfersel0[2:0] | Output |
Electrical idle entry inference mechanism selection. The following encodings are defined:
|
phystatus0 |
Input |
PHY status <n>. This signal communicates completion of several PHY requests. |
powerdown0[1:0] |
Output |
Power down <n>. This signal requests the PHY to change its power state to the specified state (P0, P0s, P1, or P2). |
rate[1:0] | Output |
Controls the link signaling rate. The following encodings are defined:
|
rxblkst0 | Input |
For Gen3 operation, indicates the start of a block in the receive direction. |
rxdata0[31:0] |
Input |
Receive data. This bus receives data on lane <n>. |
rxdatak0[3:0] | Input |
Data/Control bits for the symbols of receive data. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only. |
rxelecidle0 |
Input |
Receive electrical idle <n>. When asserted, indicates detection of an electrical idle. |
rxpolarity0 |
Output |
Receive polarity <n>. This signal instructs the PHY layer to invert the polarity of the 8B/10B receiver decoding block. |
rxstatus0[2:0] |
Input |
Receive status <n>. This signal encodes receive status and error codes for the receive data stream and receiver detection. |
rxvalid0 |
Input |
Receive valid <n>. This symbol indicates symbol lock and valid data on rxdata <n> and rxdatak <n>. |
sim_pipe_ltssmstate0[4:0] | Input and Output |
LTSSM state: The LTSSM state machine encoding defines the following states:
|
sim_pipe_pclk_in | Input |
This clock is used for PIPE simulation only, and is derived from the refclk. It is the PIPE interface clock used for PIPE mode simulation. |
sim_pipe_rate[1:0] | Input |
Specifies the data rate. The 2-bit encodings have the following meanings:
|
txblkst |
For Gen3 operation, indicates the start of a block in the transmit direction. | |
txcompl0 |
Output |
Transmit compliance <n>. This signal forces the running disparity to negative in compliance mode (negative COM character). |
txdata0[31:0] | Output |
Transmit data. This bus transmits data on lane <n>. |
txdatak0[3:0] | Output |
Transmit data control <n>. This signal serves as the control bit for txdata <n>. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only. |
txdataskip0 | Output |
For Gen3 operation. Allows the MAC to instruct the TX interface to ignore the TX data interface for one clock cycle. The following encodings are defined:
|
txdeemph0 | Output |
Transmit de-emphasis selection. The value for this signal is set based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value. |
txdetectrx0 |
Output |
Transmit detect receive <n>. This signal tells the PHY layer to start a receive detection operation or to begin loopback. |
txelecidle0 |
Output |
Transmit electrical idle <n>. This signal forces the TX output to electrical idle. |
txmargin0[2:0] |
Output |
Transmit VOD margin selection. The value for this signal is based on the value from the Link Control 2 Register. Available for simulation only. |
txswing0 | Output |
When asserted, indicates full swing for the transmitter voltage. When deasserted indicates half swing. |
txsynchd0 [1:0] | Output |
For Gen3 operation, specifies the block type. The following encodings are defined:
|