Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

Download PDF
ID 683686
Date 9/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the SR-IOV Design Example 3. Parameter Settings 4. Physical Layout 5. Interfaces and Signal Descriptions 6. Registers 7. Reset and Clocks 8. Programming and Testing SR-IOV Bridge MSI Interrupts 9. Error Handling 10. IP Core Architecture 11. Design Implementation 12. Debugging 13. Document Revision History A. Transaction Layer Packet (TLP) Header Formats B. Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
1. Datasheet x
1.1. Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Debug Features 1.5. IP Core Verification 1.6. Performance and Resource Utilization 1.7. Recommended Speed Grades for SR-IOV Interface
1.1. Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet x
1.1.1. SR-IOV Features
1.5. IP Core Verification x
1.5.1. Compatibility Testing Environment
2. Getting Started with the SR-IOV Design Example x
2.1. Directory Structure for Arria® 10 SR-IOV Design Example 2.2. Design Components for the SR-IOV Design Example 2.3. Generating the SR-IOV Design Example 2.4. Compiling and Simulating the Design for SR-IOV
3. Parameter Settings x
3.1. Parameters 3.2. Arria® 10 Avalon-ST Settings 3.3. Arria® 10 SR-IOV System Settings 3.4. Base Address Register (BAR) Settings 3.5. SR-IOV Device Identification Registers 3.6. Arria® 10 Interrupt Capabilities 3.7. Physical Function TLP Processing Hints (TPH) 3.8. Address Translation Services (ATS) 3.9. PCI Express and PCI Capabilities Parameters 3.10. PHY Characteristics 3.11. Example Designs
3.9. PCI Express and PCI Capabilities Parameters x
3.9.1. PCI Express and PCI Capabilities 3.9.2. Error Reporting 3.9.3. Link Capabilities 3.9.4. Slot Capabilities 3.9.5. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions x
5.1. Avalon-ST TX Interface 5.2. Component-Specific Avalon-ST Interface Signals 5.3. Avalon-ST RX Interface 5.4. BAR Hit Signals 5.5. Configuration Status Interface 5.6. Clock Signals 5.7. Function-Level Reset (FLR) Interface 5.8. SR-IOV Interrupt Interface 5.9. Configuration Extension Bus (CEB) Interface 5.10. Implementing MSI-X Interrupts 5.11. Control Shadow Interface 5.12. Local Management Interface (LMI) Signals 5.13. Reset, Status, and Link Training Signals 5.14. Hard IP Reconfiguration Interface 5.15. Serial Data Signals 5.16. Test Signals 5.17. PIPE Interface Signals 5.18. Arria® 10 Development Kit Conduit Interface
5.9. Configuration Extension Bus (CEB) Interface x
5.9.1. Vital Product Data (VPD) Capability
5.9.1. Vital Product Data (VPD) Capability x
5.9.1.1. Determine the Pointer Address of an External Capability Register 5.9.1.2. VPD Capability Implementation
6. Registers x
6.1. Addresses for Physical and Virtual Functions 6.2. Correspondence between Configuration Space Registers and the PCIe Specification 6.3. PCI and PCI Express Configuration Space Registers 6.4. MSI Registers 6.5. MSI-X Capability Structure 6.6. Power Management Capability Structure 6.7. PCI Express Capability Structure 6.8. Advanced Error Reporting (AER) Enhanced Capability Header Register 6.9. Uncorrectable Error Status Register 6.10. Uncorrectable Error Mask Register 6.11. Uncorrectable Error Severity Register 6.12. Correctable Error Status Register 6.13. Correctable Error Mask Register 6.14. Advanced Error Capabilities and Control Register 6.15. Header Log Registers 0-3 6.16. SR-IOV Virtualization Extended Capabilities Registers 6.17. Virtual Function Registers
6.3. PCI and PCI Express Configuration Space Registers x
6.3.1. Type 0 Configuration Space Registers 6.3.2. PCI and PCI Express Configuration Space Register Content 6.3.3. Interrupt Line and Interrupt Pin Register
6.16. SR-IOV Virtualization Extended Capabilities Registers x
6.16.1. SR-IOV Virtualization Extended Capabilities Registers Address Map 6.16.2. ARI Enhanced Capability Header 6.16.3. SR-IOV Enhanced Capability Registers 6.16.4. Initial VFs and Total VFs Registers 6.16.5. VF Device ID Register 6.16.6. Page Size Registers 6.16.7. VF Base Address Registers (BARs) 0-5 6.16.8. Secondary PCI Express Extended Capability Header 6.16.9. Lane Status Registers 6.16.10. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Function Level Reset (FLR) 7.3. Clocks
7.3. Clocks x
7.3.1. Clock Domains 7.3.2. Clock Summary
7.3.1. Clock Domains x
7.3.1.1. coreclkout_hip 7.3.1.2. pld_clk
8. Programming and Testing SR-IOV Bridge MSI Interrupts x
8.1. Setting Up and Verifying MSI Interrupts 8.2. Masking MSI Interrupts 8.3. Dropping a Pending MSI Interrupt
9. Error Handling x
9.1. Physical Layer Errors 9.2. Data Link Layer Errors 9.3. Transaction Layer Errors 9.4. Error Reporting and Data Poisoning 9.5. Uncorrectable and Correctable Error Status Bits
10. IP Core Architecture x
10.1. PCI Express Protocol Stack 10.2. Data Link Layer 10.3. Physical Layer 10.4. Top-Level Interfaces 10.5. Arria® 10 Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
10.4. Top-Level Interfaces x
10.4.1. Avalon-ST Interface 10.4.2. Clocks and Reset 10.4.3. Interrupts 10.4.4. PIPE
11. Design Implementation x
11.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 11.2. Recommended Reset Sequence to Avoid Link Training Issues 11.3. SDC Timing Constraints
12. Debugging x
12.1. Setting Up Simulation 12.2. Simulation Fails To Progress Beyond Polling.Active State 12.3. Hardware Bring-Up Issues 12.4. Link Training 12.5. Creating a Signal Tap Debug File to Match Your Design Hierarchy 12.6. Use Third-Party PCIe Analyzer 12.7. BIOS Enumeration Issues
12.1. Setting Up Simulation x
12.1.1. Changing Between Serial and PIPE Simulation 12.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants 12.1.3. Viewing the Important PIPE Interface Signals 12.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 12.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
13. Document Revision History x
13.1. Document Revision History for the Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
1. Datasheet
2. Getting Started with the SR-IOV Design Example
3. Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Programming and Testing SR-IOV Bridge MSI Interrupts
9. Error Handling
10. IP Core Architecture
11. Design Implementation
12. Debugging
13. Document Revision History
A. Transaction Layer Packet (TLP) Header Formats
B. Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive

6.7. PCI Express Capability Structure

Figure 47. PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.
Table 56.  PCI Express Capability Register - 0x080
Bits Description Default Value Access
[31:19] Reserved 0 RO
[18:16] Version ID: Version of Power Management Capability. 0x3 RO
[15:8] Next Capability Pointer: Points to the PCI Express Capability. 0x80 RO
[7:0] Capability ID assigned by PCI-SIG. 0x01 RO
Table 57.   PCI Express Device Capabilities Register -0x084
Bits Description Default Value Access
[2:0] Maximum Payload Size supported by the Function. Can be configured as 000 (128 bytes) or 001 (256 bytes) Set in Platform Designer RO
[4:3] Reserved 0 RO
[5] Extended tags supported Set in Platform Designer RO
[8:6] Acceptable L0S latency Set in Platform Designer RO
[11:9] Acceptable L1 latency Set in Platform Designer RO
[14:12] Reserved 0 RO
[15] Role-Based error reporting supported 1 RO
[17:16] Reserved 0 RO
[27:18] Captured Slot Power Limit Value and Scale: Not implemented 0 RO
[28] FLR Capable. Indicates that the device has FLR capability Set in Platform Designer RO
[31:29 ] Reserved 0 RO
Table 58.   PCI Express Device Control and Status Register - 0x088
Bits Description Default Value Access
[0] Enable Correctable Error Reporting. 0 RW
[1] Enable Non-Fatal Error Reporting. 0 RW
[2] Enable Fatal Error Reporting. 0 RW
[3] Enable Unsupported Request (UR) Reporting. 0 RW
[4] Enable Relaxed Ordering. Set in Platform Designer RW
[7:5] Maximum Payload Size. 0 (128 bytes) RW
[8] Extended Tag Field Enable. 0 RW
[10:9] Reserved. 0 RO
[11] Enable No-Snoop. 1 RW
[14:12] Maximum Read Request Size. 2 (512 bytes) RW
[15] Function-Level Reset. Writing a 1 generates a Function-Level Reset for this Function if the FLR Capable bit of the Device Capabilities Register is set. This bit always reads as 0. 0 RW
[16] Correctable Error detected. 0 RW1C
[17] Non-Fatal Error detected. 0 RW1C
[18] Fatal Error detected. 0 RW1C
[19] Unsupported Request detected. 0 RW1C
[20] Reserved. 0 RO
[21] Transaction Pending: Indicates that a Non- Posted request issued by this Function is still pending. 0 RO
[31:22] Reserved. 0 RO
Table 59.  Link Capabilities Register - 0x08C
Bits Description Default Value Access
[3:0] Maximum Link Speed 1: 2.5 GT/s

2: 5.0 GT/s

3: 8.0 GT/s

RO
[9:4] Maximum Link Width 1, 2, 4 or 8 RO
[10] ASPM Support for L0S state Set in Platform Designer RO
[11] ASPM Support for L1 state Set in Platform Designer RO
[14:12] L0S Exit Latency Set in Platform Designer, 0x6 RO
[17:15] L1 Exit Latency Set in Platform Designer, 0x0 RO
[21:18] Reserved 0 RO
[22] ASPM Optionality Compliance 1 RO
[31:23] Reserved 0 RO
Table 60.   Link Control and Status Register - 0x090
Bits Description Default Value Access
[1:0] ASPM Control 0 RW
[2] Reserved 0 R O
[3] Read Completion Boundary 0 RW
[5:4] Reserved 0 RO
[6] Common Clock Configuration 0 RW
[7] Extended Synch 0 RW
[15:8] Reserved 0 RO
[19:16] Negotiated Link Speed 0 RO
[25:20] Negotiated Link Width 0 RO
[27:26] Reserved 0 RO
[28] Slot Clock Configuration Set in Platform Designer RO
[31:29] Reserved 0 RO
Table 61.   PCI Express Device Capabilities 2 Register - 0x0A4
Bits Description Default Value Access
[3:0] Completion Timeout ranges Set in Platform Designer RO
[4] Completion Timeout disable supported Set in Platform Designer RO
[31:5] Reserved 0 RO
Table 62.   PCI Express Device Control 2 and Status 2 Register - 0x0A8
Bits Description Default Value Access
[3:0] Completion Timeout value 0xF RW
[4] Completion Timeout disable 1 RW
[5] Reserved 0 RO
[6] Atomic Operation Requester Enable 0 RW
[31:7] Reserved 0 RO
Table 63.   Link Capabilities 2 Register - 0x0AC
Bits Description Default Value Access
[0] Reserved 0 RO
[3:1] Link speeds supported

1 (2.5 GT/s)

3 (5.0 GT/s)

7 (8.0 GT/s)

Set in Platform Designer 		RO
[31:4] Reserved 0 RO
Table 64.  Link Control 2 and Status 2 Register - 0x0B0
Bits Description Default Value Access
[3:0] Target Link Speed

1: Gen1

2: Gen2

3: Gen3

RWS
[4] Enter Compliance 0 RWS
[5] Hardware Autonomous Speed Disable 0 RW
[6] Selectable De-emphasis 0 RO
[9:7] Transmit Margin 0 RWS
[10] Enter Modified Compliance 0 RWS
[11] Compliance SOS 0 RWS
[15:12] Compliance Preset/De-emphasis 0 RWS
[16] Current De-emphasis Level 0 RO
[17] Equalization Complete 0 RO
[18] Equalization Phase 1 Successful 0 RO
[19] Equalization Phase 2 Successful 0 RO
[20] Equalization Phase 3 Successful 0 RO
[21] Link Equalization Request 0 RW1C
[31:22] Reserved 0 RO
Level Two Title