Visible to Intel only — GUID: nik1410905527440
Ixiasoft
Visible to Intel only — GUID: nik1410905527440
Ixiasoft
5.6. Clock Signals
Signal |
Direction |
Description |
---|---|---|
refclk | Input |
Reference clock for the Arria® 10 Hard IP for PCI Express. It must have the frequency specified under the System Settings heading in the parameter editor. |
pld_clk | Input |
Clocks the Application Layer. You can drive this clock with coreclkout_hip. If you drive pld_clk with another clock source, it must be equal to or faster than coreclkout. All the interfaces and internal modules of the SR-IOV Bridge use this clock as the reference clock. Its frequency is 125 or 250 MHz. |
coreclkout_hip | Output |
This is a fixed frequency clock used by the Data Link and Transaction Layers. To meet PCI Express link bandwidth constraints, this clock has minimum frequency requirements as listed in coreclkout_hip Values for All Parameterizations in the Reset and Clocks chapter . |
Refer to Arria® 10 Hard IP for PCI Express Clock Domains in the Reset and Clocks chapter for more information about clocks.