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1. Datasheet
2. Getting Started with the SR-IOV Design Example
3. Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Programming and Testing SR-IOV Bridge MSI Interrupts
9. Error Handling
10. IP Core Architecture
11. Design Implementation
12. Debugging
13. Document Revision History
A. Transaction Layer Packet (TLP) Header Formats
B. Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
3.1. Parameters
3.2. Arria® 10 Avalon-ST Settings
3.3. Arria® 10 SR-IOV System Settings
3.4. Base Address Register (BAR) Settings
3.5. SR-IOV Device Identification Registers
3.6. Arria® 10 Interrupt Capabilities
3.7. Physical Function TLP Processing Hints (TPH)
3.8. Address Translation Services (ATS)
3.9. PCI Express and PCI Capabilities Parameters
3.10. PHY Characteristics
3.11. Example Designs
5.1. Avalon-ST TX Interface
5.2. Component-Specific Avalon-ST Interface Signals
5.3. Avalon-ST RX Interface
5.4. BAR Hit Signals
5.5. Configuration Status Interface
5.6. Clock Signals
5.7. Function-Level Reset (FLR) Interface
5.8. SR-IOV Interrupt Interface
5.9. Configuration Extension Bus (CEB) Interface
5.10. Implementing MSI-X Interrupts
5.11. Control Shadow Interface
5.12. Local Management Interface (LMI) Signals
5.13. Reset, Status, and Link Training Signals
5.14. Hard IP Reconfiguration Interface
5.15. Serial Data Signals
5.16. Test Signals
5.17. PIPE Interface Signals
5.18. Arria® 10 Development Kit Conduit Interface
6.1. Addresses for Physical and Virtual Functions
6.2. Correspondence between Configuration Space Registers and the PCIe Specification
6.3. PCI and PCI Express Configuration Space Registers
6.4. MSI Registers
6.5. MSI-X Capability Structure
6.6. Power Management Capability Structure
6.7. PCI Express Capability Structure
6.8. Advanced Error Reporting (AER) Enhanced Capability Header Register
6.9. Uncorrectable Error Status Register
6.10. Uncorrectable Error Mask Register
6.11. Uncorrectable Error Severity Register
6.12. Correctable Error Status Register
6.13. Correctable Error Mask Register
6.14. Advanced Error Capabilities and Control Register
6.15. Header Log Registers 0-3
6.16. SR-IOV Virtualization Extended Capabilities Registers
6.17. Virtual Function Registers
6.16.1. SR-IOV Virtualization Extended Capabilities Registers Address Map
6.16.2. ARI Enhanced Capability Header
6.16.3. SR-IOV Enhanced Capability Registers
6.16.4. Initial VFs and Total VFs Registers
6.16.5. VF Device ID Register
6.16.6. Page Size Registers
6.16.7. VF Base Address Registers (BARs) 0-5
6.16.8. Secondary PCI Express Extended Capability Header
6.16.9. Lane Status Registers
6.16.10. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
12.1.1. Changing Between Serial and PIPE Simulation
12.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants
12.1.3. Viewing the Important PIPE Interface Signals
12.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
12.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
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10.2. Data Link Layer
The Data Link Layer is located between the Transaction Layer and the Physical Layer. It maintains packet integrity and communicates (by DLL packet transmission) at the PCI Express link level.
The DLL implements the following functions:
- Link management through the reception and transmission of DLL Packets (DLLP), which are used for the following functions:
- Power management of DLLP reception and transmission
- To transmit and receive ACK/NAK packets
- Data integrity through generation and checking of CRCs for TLPs and DLLPs
- TLP retransmission in case of NAK DLLP reception or replay timeout, using the retry (replay) buffer
- Management of the retry buffer
- Link retraining requests in case of error through the Link Training and Status State Machine (LTSSM) of the Physical Layer
Figure 55. Data Link Layer
The DLL has the following sub-blocks:
- Data Link Control and Management State Machine—This state machine connects to both the Physical Layer’s LTSSM state machine and the Transaction Layer. It initializes the link and flow control credits and reports status to the Transaction Layer.
- Power Management—This function handles the handshake to enter low power mode. Such a transition is based on register values in the Configuration Space and received Power Management (PM) DLLPs. All of the Arria® 10 Hard IP for PCIe IP core variants do not support low power modes.
- Data Link Layer Packet Generator and Checker—This block is associated with the DLLP’s 16-bit CRC and maintains the integrity of transmitted packets.
- Transaction Layer Packet Generator—This block generates transmit packets, including a sequence number and a 32-bit Link CRC (LCRC). The packets are also sent to the retry buffer for internal storage. In retry mode, the TLP generator receives the packets from the retry buffer and generates the CRC for the transmit packet.
- Retry Buffer—The retry buffer stores TLPs and retransmits all unacknowledged packets in the case of NAK DLLP reception. In case of ACK DLLP reception, the retry buffer discards all acknowledged packets.
- ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequence number of transmitted packets.
- Transaction Layer Packet Checker—This block checks the integrity of the received TLP and generates a request for transmission of an ACK/NAK DLLP.
- TX Arbitration—This block arbitrates transactions, prioritizing in the following order:
- Initialize FC Data Link Layer packet
- ACK/NAK DLLP (high priority)
- Update FC DLLP (high priority)
- PM DLLP
- Retry buffer TLP
- TLP
- Update FC DLLP (low priority)
- ACK/NAK FC DLLP (low priority)