Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

ID 683686
Date 9/12/2024
Public
Document Table of Contents

7.3.2. Clock Summary

Table 95.  Clock Summary

Name

Frequency

Clock Domain

coreclkout_hip

62.5, 125 or 250 MHz

Avalon‑ST interface between the Transaction and Application Layers.

pld_clk

125 or 250 MHz

Application and Transaction Layers.

refclk

100 MHz

SERDES (transceiver). Dedicated free running input clock to the SERDES block.