Visible to Intel only — GUID: hco1405703848415
Ixiasoft
Process Description
Tutorial Steps
2.1. Step 1: Getting Started
2.2. Step 2: Preparing the Base Revision
2.3. Step 3: Preparing the Implementation Revisions for Debugging
2.4. Step 4: Configuring Signal Tap Logic Analyzer
2.5. Step 5: Generating Programming Files
2.6. Step 6: Programming the FPGA Device
2.7. Step 7: Performing Data Acquisition
Visible to Intel only — GUID: hco1405703848415
Ixiasoft
2. Tutorial Walkthrough
This tutorial describes preparing the blinking_led design for debug with the Signal Tap Logic Analyzer.
This Application Note does not describe turning a non-PR design to a PR design. Refer to AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board for examples of the following tasks:
- Creating a design partition
- Allocating placement and routing regions for a PR partition
- Defining personas
- Creating project revisions
- Preparing PR implementation revisions
Process Description
To tap signals in a PR design, you extend the debug fabric to the PR regions when creating the base revision, and then define debug components for the implementation revisions.
Tutorial Steps
This tutorial includes the following steps:
- Step 1: Getting Started
- Step 2: Preparing the Base Revision
- Step 3: Preparing the Implementation Revisions for Debugging
- Tapping Signals in the Implementation Persona
- Configuring Data Acquisition
- Setting Trigger Conditions
- Step 5: Generating Programming Files
- Step 6: Programming the FPGA Device
- Step 7: Performing Data Acquisition