AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

Download PDF
ID 683662
Date 1/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Tutorial Overview 2. Tutorial Walkthrough 3. Tutorial Results 4. Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design
1. Tutorial Overview x
1.1. PR Debug Considerations 1.2. Tutorial Software and Hardware Requirements 1.3. Tutorial Design Description 1.4. Downloading the Tutorial Design
1.4. Downloading the Tutorial Design x
1.4.1. Tutorial Design Files
2. Tutorial Walkthrough x
2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debugging 2.4. Step 4: Configuring Signal Tap Logic Analyzer 2.5. Step 5: Generating Programming Files 2.6. Step 6: Programming the FPGA Device 2.7. Step 7: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision x
2.2.1. Preparing the Static Region 2.2.2. Preparing the Default PR Persona
2.4. Step 4: Configuring Signal Tap Logic Analyzer x
2.4.1. Tapping Signals in the Implementation Persona 2.4.2. Configuring Data Acquisition 2.4.3. Setting Trigger Conditions
2.4.2. Configuring Data Acquisition x
2.4.2.1. Add Acquisition Clock 2.4.2.2. Add Storage Parameters
3. Tutorial Results x
3.1. Waveforms for Slow Implementation 3.2. Waveforms for Default Implementation 3.3. Waveforms for Empty Implementation
1. Tutorial Overview
2. Tutorial Walkthrough
3. Tutorial Results
4. Document Revision History for AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

1.1. PR Debug Considerations

Debugging a PR design requires planning. Before compiling, you must decide whether to tap signals in the static region, which PR region you want to debug, and which personas in the PR region you want to debug.

If you have multiple personas in your design, you must also instantiate the Intel® Configuration Reset Release Endpoint to Debug Logic IP in each PR region. This IP ensures proper function by providing a reset signal to debug logic, such as Signal Tap, after partial reconfiguration. This reset signal must be high during configuration, and then this reset signal must go low once partial reconfiguration is complete. You must not release this reset signal after releasing the PR logic reset. The time of this reset release affects the Signal Tap power-up trigger feature. The reset signal must stay low until the next reconfiguration.

Note: Do not assert this reset input while the device is in the user operational mode. Asserting this reset input while the device is in the user operational mode results in incorrect operation in Signal Tap and other debugging tools.
If you omit the Intel Configuration Reset Release Endpoint to Debug Logic IP from your PR design, The Compiler issues the following error message: 
Error(11176): Alt_sld_fab_1.alt_sld_fab_1.alt_sld_fab_1: The Intel Configuration Reset Release 
Endpoint to Debug Logic IP must be instantiated to provide the reset signal to the debug logic, 
such as Signal Tap, etc. after the partial configuration is performed.

To ensure visibility, the debugging fabric must extend to all the regions that you want to tap. The Intel® Quartus® Prime software enables you to extend the debug fabric by using debug bridge components: the SLD JTAG Bridge Agent Intel® FPGA IP and the SLD JTAG Bridge Host Intel® FPGA IP.

To incorporate these components to the design, for each PR region in the design that you want to debug:

  1. Instantiate the SLD JTAG Bridge Agent Intel FPGA IP in the static region.
  2. Instantiate the SLD JTAG Bridge Host Intel FPGA IP and the Intel Configuration Reset Release Endpoint to Debug Logic in the PR region of the default persona.
  3. Instantiate the SLD JTAG Bridge Host Intel FPGA IP and the Intel Configuration Reset Release Endpoint to Debug Logic on the implementation revisions that you want to debug.
Figure 1. Debug Fabric in PR Design with Signal Tap The figure shows in solid outline the entities that you instantiate manually, and in dashed outline the entities that the Compiler instantiates automatically.

SLD JTAG Bridge Index

The index is an attribute of the SLD JTAG Bridge Agent that uniquely identifies bridge agents present in the design. You can find information regarding the bridge index in the synthesis report (<base revision>.syn.rpt), by looking under JTAG Bridge Agent Instance Information. The bridge index for the root partition is always None.

Related Information
Level Two Title