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Key Advantages of MAX® 10 Devices
Summary of MAX® 10 Device Features
MAX® 10 Device Ordering Information
MAX® 10 Device Maximum Resources
MAX® 10 Devices I/O Resources Per Package
MAX® 10 Vertical Migration Support
Logic Elements and Logic Array Blocks
Analog-to-Digital Converter
User Flash Memory
Embedded Multipliers and Digital Signal Processing Support
Embedded Memory Blocks
Clocking and PLL
FPGA General Purpose I/O
External Memory Interface
Configuration
Power Management
Revision History for the MAX® 10 FPGA Device Overview
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MultiVolt I/O Interface
The MultiVolt I/O interface feature of MAX® 10 devices maximizes pin utilization per I/O bank. You can connect input signals of different voltages to the same I/O bank.
Examples:
- I/O banks with 3.3 V VCCIO—you can connect 3.3 V, 3.0 V, and 2.5 V input signals
- I/O banks with 3.0 V VCCIO—you can connect 3.3 V, 3.0 V, and 2.5 V input signals
| I/O Bank VCCIO (V) | Supported Input Signal |
|---|---|
| 3.3 | 3.3 V, 3.0 V, 2.5 V LVCMOS/LVTTL |
| 3.0 | 3.3 V, 3.0 V, 3.0 V PCI, 2.5 V LVCMOS/LVTTL |
| 2.5 | 3.3 V, 3.0 V, 2.5 V LVCMOS/LVTTL, SSTL-2, 2.5 V LVDS |
| 1.8 | 1.8 V LVCMOS, SSTL-18, HSTL-18, 1.8 V LVDS, 1.5 V LVCMOS |
| 1.5 | 1.8 V LVCMOS, 1.5 V LVCMOS, SSTL-15, HSTL-15 |
| 1.35 | SSTL-135 |
| 1.2 | 1.2 V LVCMOS, HSTL-12, HSUL-12 |
| 1.0 | 1.0 V LVCMOS |
For the detailed requirements, refer to the MAX® 10 General-Purpose I/O User Guide.
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