MAX® 10 FPGA Device Overview

Download PDF
ID 683658
Date 3/10/2025
Public

Visible to Intel only — GUID: myt1399256489601

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Overview
MAX® 10 FPGA Device Overview x
Key Advantages of MAX® 10 Devices Summary of MAX® 10 Device Features MAX® 10 Device Ordering Information MAX® 10 Device Maximum Resources MAX® 10 Devices I/O Resources Per Package MAX® 10 Vertical Migration Support Logic Elements and Logic Array Blocks Analog-to-Digital Converter User Flash Memory Embedded Multipliers and Digital Signal Processing Support Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O External Memory Interface Configuration Power Management Revision History for the MAX® 10 FPGA Device Overview
MAX® 10 Device Ordering Information x
MAX® 10 Device Feature Options
MAX® 10 Vertical Migration Support x
MAX® 10 I/O Vertical Migration Support MAX® 10 ADC Vertical Migration Support
FPGA General Purpose I/O x
MultiVolt I/O Interface LVDS Tunneling Protocol and Interface
Configuration x
Remote System Update Hitless Update
MAX® 10 FPGA Device Overview

MAX® 10 Device Feature Options

Table 3.   Feature Options for MAX® 10 Devices
Option Feature
Compact Devices with core architecture featuring single configuration image with self-configuration capability
Flash Devices with core architecture featuring:
  • Dual configuration image with self-configuration capability
  • Remote system upgrade capability
  • Memory initialization
Analog Devices with core architecture featuring:
  • Dual configuration image with self-configuration capability
  • Remote system upgrade capability
  • Memory initialization
  • Integrated ADC
Level Two Title