MAX® 10 FPGA Device Overview

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ID 683658
Date 3/10/2025
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Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Overview
MAX® 10 FPGA Device Overview x
Key Advantages of MAX® 10 Devices Summary of MAX® 10 Device Features MAX® 10 Device Ordering Information MAX® 10 Device Maximum Resources MAX® 10 Devices I/O Resources Per Package MAX® 10 Vertical Migration Support Logic Elements and Logic Array Blocks Analog-to-Digital Converter User Flash Memory Embedded Multipliers and Digital Signal Processing Support Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O External Memory Interface Configuration Power Management Revision History for the MAX® 10 FPGA Device Overview
MAX® 10 Device Ordering Information x
MAX® 10 Device Feature Options
MAX® 10 Vertical Migration Support x
MAX® 10 I/O Vertical Migration Support MAX® 10 ADC Vertical Migration Support
FPGA General Purpose I/O x
MultiVolt I/O Interface LVDS Tunneling Protocol and Interface
Configuration x
Remote System Update Hitless Update
MAX® 10 FPGA Device Overview

External Memory Interface

Dual-supply MAX® 10 devices feature external memory interfaces solution that uses the I/O elements on the right side of the devices together with the UniPHY IP.

With this solution, you can create external memory interfaces to 16-bit SDRAM components with error correction coding (ECC).

Note: The external memory interface feature is available only for dual-supply MAX® 10 devices.
Table 13.  External Memory Interface Performance
External Memory Interface6 I/O Standard Maximum Width Maximum Frequency (MHz)
DDR3 SDRAM SSTL-15 16 bit + 8 bit ECC 303
DDR3L SDRAM SSTL-135 16 bit + 8 bit ECC 303
DDR2 SDRAM SSTL-18 16 bit + 8 bit ECC 200
LPDDR2 SDRAM HSUL-12 16 bit without ECC 200 7
Related Information
6 The device hardware supports SRAM. Use your own design to interface with SRAM devices.
7 To achieve the specified performance, constrain the memory device I/O and core power supply variation to within ±3%. By default, the frequency is 167 MHz.
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