MAX® 10 FPGA Device Overview

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ID 683658
Date 6/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® MAX® 10 FPGA Device Overview
Intel® MAX® 10 FPGA Device Overview x
Key Advantages of Intel® MAX® 10 Devices Summary of Intel® MAX® 10 Device Features Intel® MAX® 10 Device Ordering Information Intel® MAX® 10 Device Maximum Resources Intel® MAX® 10 Devices I/O Resources Per Package Intel® MAX® 10 Vertical Migration Support Logic Elements and Logic Array Blocks Analog-to-Digital Converter User Flash Memory Embedded Multipliers and Digital Signal Processing Support Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O External Memory Interface Configuration Power Management Document Revision History for Intel® MAX® 10 FPGA Device Overview
Intel® MAX® 10 Device Ordering Information x
Intel® MAX® 10 Device Feature Options
Intel® MAX® 10 Vertical Migration Support x
Intel® MAX® 10 I/O Vertical Migration Support Intel® MAX® 10 ADC Vertical Migration Support
Intel® MAX® 10 FPGA Device Overview

Embedded Memory Blocks

The embedded memory structure consists of M9K memory blocks columns. Each M9K memory block of a Intel® MAX® 10 device provides 9 Kb of on-chip memory capable of operating at up to 284 MHz. The embedded memory structure consists of M9K memory blocks columns. Each M9K memory block of a Intel® MAX® 10 device provides 9 Kb of on-chip memory. You can cascade the memory blocks to form wider or deeper logic structures.

You can configure the M9K memory blocks as RAM, FIFO buffers, or ROM.

The Intel® MAX® 10 device memory blocks are optimized for applications such as high throughput packet processing, embedded processor program, and embedded data storage.

Table 10.  M9K Operation Modes and Port Widths
Operation Modes Port Widths
Single port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
Simple dual port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
True dual port ×1, ×2, ×4, ×8, ×9, ×16, and ×18
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