MAX® 10 FPGA Device Overview

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ID 683658
Date 6/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® MAX® 10 FPGA Device Overview
Intel® MAX® 10 FPGA Device Overview x
Key Advantages of Intel® MAX® 10 Devices Summary of Intel® MAX® 10 Device Features Intel® MAX® 10 Device Ordering Information Intel® MAX® 10 Device Maximum Resources Intel® MAX® 10 Devices I/O Resources Per Package Intel® MAX® 10 Vertical Migration Support Logic Elements and Logic Array Blocks Analog-to-Digital Converter User Flash Memory Embedded Multipliers and Digital Signal Processing Support Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O External Memory Interface Configuration Power Management Document Revision History for Intel® MAX® 10 FPGA Device Overview
Intel® MAX® 10 Device Ordering Information x
Intel® MAX® 10 Device Feature Options
Intel® MAX® 10 Vertical Migration Support x
Intel® MAX® 10 I/O Vertical Migration Support Intel® MAX® 10 ADC Vertical Migration Support
Intel® MAX® 10 FPGA Device Overview

Intel® MAX® 10 I/O Vertical Migration Support

Figure 2. Migration Capability Across Intel® MAX® 10 Devices
  • The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Non-migratable devices are omitted. Some packages have several migration paths. Devices with lesser I/O resources in the same path have lighter shades.
  • To achieve the full I/O migration across product lines in the same migration path, restrict I/Os usage to match the product line with the lowest I/O count.


Note: Before starting migration work, Intel recommends that you verify the pin migration compatibility through the Pin Migration View window in the Intel® Quartus® Prime software Pin Planner. For example, not all Intel® MAX® 10 devices support 1.0 V I/O.
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