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Key Advantages of Intel® MAX® 10 Devices
Summary of Intel® MAX® 10 Device Features
Intel® MAX® 10 Device Ordering Information
Intel® MAX® 10 Device Maximum Resources
Intel® MAX® 10 Devices I/O Resources Per Package
Intel® MAX® 10 Vertical Migration Support
Logic Elements and Logic Array Blocks
Analog-to-Digital Converter
User Flash Memory
Embedded Multipliers and Digital Signal Processing Support
Embedded Memory Blocks
Clocking and PLL
FPGA General Purpose I/O
External Memory Interface
Configuration
Power Management
Document Revision History for Intel® MAX® 10 FPGA Device Overview
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Logic Elements and Logic Array Blocks
The LAB consists of 16 logic elements (LE) and a LAB-wide control block. An LE is the smallest unit of logic in the Intel® MAX® 10 device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables.
Figure 4. Intel® MAX® 10 Device Family LEs