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Ixiasoft
Overview of HPS Modules
HPS MPU Subsystem Differences
Stratix 10 HPS Interface to SDM
Booting and Configuration Differences
HPS Cache Coherency Controller Differences
HPS System Memory Management Differences
HPS On-Chip RAM Differences
HPS Error Correction Differences
HPS DMA Controller Differences
HPS Clock Manager Differences
HPS Reset Manager Differences
HPS FPGA Manager Differences
HPS System Manager Differences
HPS Scan Manager Differences
HPS Security Feature Differences
HPS Interconnect Differences
HPS-FPGA Bridge Differences
HPS General Purpose I/O Interface Differences
HPS I/O Configuration Differences
HPS SDRAM Controller Subsystem Differences
HPS NAND Flash Controller Differences
HPS SD/MMC Controller Differences
HPS Quad SPI Flash Controller Differences
HPS USB 2.0 OTG Controller Differences
HPS EMAC Differences
HPS SPI Controller Differences
HPS I2C Controller Differences
HPS UART Controller Differences
HPS CAN Controller Differences
HPS Timer Differences
HPS Watchdog Timer Differences
HPS CoreSight Debug and Trace Differences
Document Revision History
Visible to Intel only — GUID: cru1463082719713
Ixiasoft
HPS SPI Controller Differences
| SPI Controller Feature | Cyclone V SoC | Arria V SoC | Arria 10 SoC | Stratix 10 SoC |
|---|---|---|---|---|
| Synopsys IP Version | 3.20a | 3.20a | 3.22a | 4.00a |
| Number of SPI master cores | 2 | 2 | 2 | 2 |
| Number of SPI slave cores | 2 | 2 | 2 | 2 |
| Maximum master clock rate | 60 MHz | 60 MHz | 60 MHz | 60 MHz |
| Maximum slave clock rate | 50 MHz | 50 MHz | 50 MHz | 33.33 MHz |
| Programmable data frame size | 4 to 16 bits | 4 to 16 bits | 4 to 16 bits | 4 to 32 bits |
| SPI master bit rate clock ratio | Fspi_m_clk ≥ 2 × max(Fsclk_out) | |||
| SPI slave bit rate clock ratio | Fl4_main_clk ≥ 8 × max(Fsclk_in) | Fl4_main_clk ≥ 12 × max(Fsclk_in) | ||
| Toggle slave select signal between frames when in SPI mode and SCPH=0? | Yes | Yes | Yes | No (slave select signal stays low during data frames transfer) |