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Ixiasoft
Overview of HPS Modules
HPS MPU Subsystem Differences
Stratix 10 HPS Interface to SDM
Booting and Configuration Differences
HPS Cache Coherency Controller Differences
HPS System Memory Management Differences
HPS On-Chip RAM Differences
HPS Error Correction Differences
HPS DMA Controller Differences
HPS Clock Manager Differences
HPS Reset Manager Differences
HPS FPGA Manager Differences
HPS System Manager Differences
HPS Scan Manager Differences
HPS Security Feature Differences
HPS Interconnect Differences
HPS-FPGA Bridge Differences
HPS General Purpose I/O Interface Differences
HPS I/O Configuration Differences
HPS SDRAM Controller Subsystem Differences
HPS NAND Flash Controller Differences
HPS SD/MMC Controller Differences
HPS Quad SPI Flash Controller Differences
HPS USB 2.0 OTG Controller Differences
HPS EMAC Differences
HPS SPI Controller Differences
HPS I2C Controller Differences
HPS UART Controller Differences
HPS CAN Controller Differences
HPS Timer Differences
HPS Watchdog Timer Differences
HPS CoreSight Debug and Trace Differences
Document Revision History
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Ixiasoft
HPS-FPGA Bridge Differences
| HPS-FPGA Bridge Feature | Cyclone V SoC | Arria V SoC | Arria 10 SoC | Stratix 10 SoC |
|---|---|---|---|---|
| HPS-to-FPGA | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit |
| Lightweight HPS-to-FPGA | 32-bit | 32-bit | 32-bit | 32-bit |
| FPGA-to-HPS | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 128-bit |
| Protocol Support | AMBA AXI-3 | AMBA AXI-3 | AMBA AXI-3 | AMBA AXI-4 + AMBA4 ACE-Lite |
| Ready latency support for improved timing | No | No | Yes | Yes |
Although the HPS and the FPGA logic can operate independently, they are tightly coupled through a high bandwidth system interconnect built from high-performance ARM® Advanced Microcontroller Bus Architecture (AMBA® ) Advanced eXtensible Interface (AXI™) bus bridges.
Bus masters on soft logic cores in the FPGA fabric have access to HPS bus slaves through the FPGA-to-HPS bridge. Similarly, HPS bus masters have access to bus slaves in the FPGA through the HPS-to-FPGA bridge.
On Cyclone V, Arria V, and Arria 10 devices, the bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to three masters in the FPGA fabric can share the HPS SDRAM controller with the processor.
On Stratix 10 devices, the FPGA-to-HPS bridge implements the AXI Coherency Extension (ACE) protocol, and passes through the CCU block.
The processor can be used to configure the core fabric under program control through a dedicated 32-bit configuration port.