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Overview of HPS Modules
HPS MPU Subsystem Differences
Stratix 10 HPS Interface to SDM
Booting and Configuration Differences
HPS Cache Coherency Controller Differences
HPS System Memory Management Differences
HPS On-Chip RAM Differences
HPS Error Correction Differences
HPS DMA Controller Differences
HPS Clock Manager Differences
HPS Reset Manager Differences
HPS FPGA Manager Differences
HPS System Manager Differences
HPS Scan Manager Differences
HPS Security Feature Differences
HPS Interconnect Differences
HPS-FPGA Bridge Differences
HPS General Purpose I/O Interface Differences
HPS I/O Configuration Differences
HPS SDRAM Controller Subsystem Differences
HPS NAND Flash Controller Differences
HPS SD/MMC Controller Differences
HPS Quad SPI Flash Controller Differences
HPS USB 2.0 OTG Controller Differences
HPS EMAC Differences
HPS SPI Controller Differences
HPS I2C Controller Differences
HPS UART Controller Differences
HPS CAN Controller Differences
HPS Timer Differences
HPS Watchdog Timer Differences
HPS CoreSight Debug and Trace Differences
Document Revision History
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Ixiasoft
HPS Cache Coherency Controller Differences
| Cache Coherency Controller Feature | Cyclone V SoC | Arria V SoC | Arria 10 SoC | Stratix 10 SoC |
|---|---|---|---|---|
| System level cache coherency | Implemented by ACP in MPCore and ACP ID mapper block | Implemented by ACP in MPCore and ACP ID mapper block | Implemented by ACP in MPCore and level 3 (L3) interconnect | Implemented by cache coherency unit (CCU) |
Cyclone V, Arria V, and Arria10 SoC devices implement system level cache coherency by exposing the MPU accelerator coherency port (ACP) to masters in the system including the FPGA fabric connected to the FPGA-to-HPS bridge. The Cyclone V and Arria V SoCs require these masters to access the ACP ID mapper while Arria 10 SoC only requires the masters to perform cacheable accesses to the MPU cache subsystem.
The Stratix 10 HPS includes a cache coherency unit that resides between the MPU and the rest of the system, allowing cacheable accesses from masters in the system, including soft IP in the FPGA fabric connected to the FPGA-to-HPS bridge. The Stratix 10 HPS CCU also performs routing functionality between the MPU, FPGA-to-HPS bridge, L3 interconnect, and SDRAM scheduler.