Differences Among Intel SoC Device Families

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ID 683648
Date 8/22/2018
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Document Table of Contents x
Differences Among Intel SoC Device Families
Differences Among Intel SoC Device Families x
Overview of HPS Modules HPS MPU Subsystem Differences Stratix 10 HPS Interface to SDM Booting and Configuration Differences HPS Cache Coherency Controller Differences HPS System Memory Management Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS Interconnect Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences HPS I/O Configuration Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/MMC Controller Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Document Revision History
Differences Among Intel SoC Device Families

HPS Error Correction Differences

Table 4.  HPS Error Correction Differences in Peripheral RAM
Error Correction Feature Cyclone V SoC Arria V SoC Arria 10 SoC Stratix 10 SoC
USB 2.0 OTG Error correction code (ECC) support Basic 10 Basic Enhanced 10 Enhanced
SD/MMC ECC support Basic Basic Enhanced Enhanced
EMAC ECC support Basic Basic Enhanced Enhanced
DMA ECC support Basic Basic Enhanced Enhanced
NAND ECC support Basic Basic Enhanced Enhanced
QSPI ECC support Basic Basic Enhanced N/A
SDRAM ECC support Basic Basic Enhanced Enhanced
ECC error injection System manager System manager ECC controller ECC controller
On-Chip RAM Read-Modify-Write Available with ECC Enabled No No No Yes
Note: The L1 and L2 caches have their own dedicated parity checking and ECC support. The SDRAM controller also has its own dedicated ECC support. For more information about cache and SDRAM ECC features for a specific device family, refer to that family's Hard Processor Technical Reference Manual.
Table 5.  Basic and Enhanced ECC Features
Feature Basic (Arria V, Cyclone V) Enhanced (Arria 10, Stratix 10)
Single-bit error detection and correction Yes Yes
Double-bit error detection Yes Yes
Indirect memory access; for RAM testing and double-bit error correction No Yes
Logs most recent error memory address No Yes
Memory initialization block implements memory initialization No Yes
Single-bit error counter with programmable counter-match interrupt No Yes
Related Information
10 See the "Basic and Enhanced ECC Features" table for the differences between basic and enhanced ECC.
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