Differences Among Intel SoC Device Families

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ID 683648
Date 8/22/2018
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Document Table of Contents x
Differences Among Intel SoC Device Families
Differences Among Intel SoC Device Families x
Overview of HPS Modules HPS MPU Subsystem Differences Stratix 10 HPS Interface to SDM Booting and Configuration Differences HPS Cache Coherency Controller Differences HPS System Memory Management Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS Interconnect Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences HPS I/O Configuration Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/MMC Controller Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Document Revision History
Differences Among Intel SoC Device Families

Booting and Configuration Differences

Table 2.  FPGA Configuration Method Differences
FPGA Configuration Method Cyclone V Arria V Arria 10 Stratix 10
NAND HPS FPGA Manager HPS FPGA Manager HPS FPGA Manager N/A
SD/MMC, Embedded Multimedia Card (eMMC) HPS FPGA Manager HPS FPGA Manager HPS FPGA Manager SDM
Active serial (AS) FPGA configuration block (CB) FPGA CB FPGA configuration subsystem (CSS) SDM
Passive serial (PS) FPGA CB FPGA CB FPGA CSS N/A
Fast passive parallel (FPP) FPGA CB, HPS FPGA Manager FPGA CB, HPS FPGA Manager FPGA CSS, HPS FPGA Manager SDM 7
Configuration via protocol (CvP) FPGA CB FPGA CB FPGA CSS SDM
JTAG FPGA CB FPGA CB FPGA CSS SDM
Supports early I/O release N/A N/A Yes Yes
Table 3.  Booting Differences
HPS Boot Feature Cyclone V SoC Arria V SoC Arria 10 SoC Stratix 10 SoC
Initial HPS Image Loader HPS Boot ROM HPS Boot ROM HPS Boot ROM SDM
HPS Boot from SD/eMMC Yes Yes Yes Yes 8
HPS Boot from NAND Yes Yes Yes Yes 8
HPS Boot from Quad SPI (QSPI) Yes Yes Yes Yes 8
HPS Boot from CvP No No No No
HPS Boot from Avalon Streaming (Avalon-ST) interface No No No Yes 8
HPS Boot from FPGA Yes Yes Yes No 9
HPS boots first, then HPS configures FPGA Yes Yes Yes Yes
HPS Boot Image Compression No No No Yes 8
HPS Boot Image Security No No Yes Yes
Related Information
7 FPP support based on Avalon® -ST
8 The initial Stratix 10 HPS bootloader is loaded by the SDM, supporting the same features and image sources as for FPGA configuration.
9 Because the Stratix 10 HPS bootloader is loaded by the SDM from the same source as the FPGA configuration image, the HPS does not have to boot from the FPGA image. This saves FPGA resources.
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