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1. Answers to Top FAQs
2. Design Optimization Overview
3. Optimizing the Design Netlist
4. Netlist Optimizations and Physical Synthesis
5. Area Optimization
6. Timing Closure and Optimization
7. Analyzing and Optimizing the Design Floorplan
8. Using the ECO Compilation Flow
9. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Intel® Quartus® Prime Pro Edition User Guides
3.1. When to Use the Netlist Viewers: Analyzing Design Problems
3.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers
3.3. RTL Viewer Overview
3.4. Technology Map Viewer Overview
3.5. Netlist Viewer User Interface
3.6. Schematic View
3.7. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows
3.8. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows
3.9. Viewing a Timing Path
3.10. Optimizing the Design Netlist Revision History
3.6.1. Display Schematics in Multiple Tabbed View
3.6.2. Schematic Symbols
3.6.3. Select Items in the Schematic View
3.6.4. Shortcut Menu Commands in the Schematic View
3.6.5. Filtering in the Schematic View
3.6.6. View Contents of Nodes in the Schematic View
3.6.7. Moving Nodes in the Schematic View
3.6.8. View LUT Representations in the Technology Map Viewer
3.6.9. Zoom Controls
3.6.10. Navigating with the Bird's Eye View
3.6.11. Partition the Schematic into Pages
3.6.12. Follow Nets Across Schematic Pages
5.2.3.1. Guideline: Optimize Source Code
5.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed
5.2.3.3. Guideline: Restructure Multiplexers
5.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting
5.2.3.5. Guideline: Use Register Packing
5.2.3.6. Guideline: Remove Fitter Constraints
5.2.3.7. Guideline: Flatten the Hierarchy During Synthesis
5.2.3.8. Guideline: Re-target Memory Blocks
5.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area
5.2.3.10. Guideline: Retarget or Balance DSP Blocks
5.2.3.11. Guideline: Use a Larger Device
5.2.3.12. Guideline: Reduce Global Signal Congestion
5.2.3.13. Guideline: Report Pipelining Information
5.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto
5.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always
5.2.4.3. Guideline: Increase Router Effort Multiplier
5.2.4.4. Guideline: Remove Fitter Constraints
5.2.4.5. Guideline: Optimize Synthesis for Routability
5.2.4.6. Guideline: Optimize Source Code
5.2.4.7. Guideline: Use a Larger Device
6.1. Optimize Multi Corner Timing
6.2. Optimize Critical Paths
6.3. Optimize Critical Chains
6.4. Design Evaluation for Timing Closure
6.5. Timing Optimization
6.6. Periphery to Core Register Placement and Routing Optimization
6.7. Scripting Support
6.8. Timing Closure and Optimization Revision History
6.5.1. Correct Design Assistant Rule Violations
6.5.2. Implement Fast Forward Timing Closure Recommendations
6.5.3. Review Timing Path Details
6.5.4. Try Optional Fitter Settings
6.5.5. Back-Annotate Optimized Assignments
6.5.6. Optimize Settings with Design Space Explorer II
6.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard
6.5.8. I/O Timing Optimization Techniques
6.5.9. Register-to-Register Timing Optimization Techniques
6.5.10. Metastability Analysis and Optimization Techniques
6.5.3.1. Report Timing
6.5.3.2. Report Logic Depth
6.5.3.3. Report Neighbor Paths
6.5.3.4. Report Register Spread
6.5.3.5. Report Route Net of Interest
6.5.3.6. Report Retiming Restrictions
6.5.3.7. Report Pipelining Information
6.5.3.8. Report CDC Viewer
6.5.3.9. Timing Closure Recommendations
6.5.3.10. Global Network Buffers
6.5.3.11. Resets and Global Networks
6.5.3.12. Suspicious Setup
6.5.3.13. Auto Shift Register Replacement
6.5.3.14. Clocking Architecture
6.5.8.1. I/O Timing Constraints
6.5.8.2. Optimize IOC Register Placement for Timing Logic Option
6.5.8.3. Fast Input, Output, and Output Enable Registers
6.5.8.4. Programmable Delays
6.5.8.5. Use PLLs to Shift Clock Edges
6.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks
6.5.8.7. Spine Clock Limitations
6.5.9.1. Optimize Source Code
6.5.9.2. Improving Register-to-Register Timing
6.5.9.3. Physical Synthesis Optimizations
6.5.9.4. Set Power Optimization During Synthesis to Normal Compilation
6.5.9.5. Optimize Synthesis for Performance, Not Area
6.5.9.6. Flatten the Hierarchy During Synthesis
6.5.9.7. Set the Synthesis Effort to High
6.5.9.8. Change Adder Tree Styles
6.5.9.9. Duplicate Registers for Fan-Out Control
6.5.9.10. Prevent Shift Register Inference
6.5.9.11. Use Other Synthesis Options Available in Your Synthesis Tool
6.5.9.12. Fitter Seed
6.5.9.13. Set Maximum Router Timing Optimization Level
6.5.9.14. Register-to-Register Timing Analysis
6.5.9.14.1. Tips for Analyzing Failing Paths
6.5.9.14.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains
6.5.9.14.3. Tips for Critical Path Analysis
6.5.9.14.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles
6.5.9.14.5. Global Routing Resources
6.5.9.14.6. Register RAMS and DSPs
7.1. Design Floorplan Analysis in Chip Planner
7.2. Defining Logic Lock Placement Constraints
7.3. Defining Virtual Pins
7.4. Using Logic Lock Regions in Combination with Design Partitions
7.5. Creating Clock Region Assignments in Chip Planner
7.6. Scripting Support
7.7. Analyzing and Optimizing the Design Floorplan Revision History
7.1.1. Starting the Chip Planner
7.1.2. Chip Planner GUI
7.1.3. Viewing Design Elements in Chip Planner
7.1.4. Finding Design Elements in the Chip Planner
7.1.5. Exploring Paths in the Chip Planner
7.1.6. Viewing Assignments in the Chip Planner
7.1.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner
7.1.8. Viewing Design Partition Placement
7.1.3.1. Viewing Architecture-Specific Design Information in Chip Planner
7.1.3.2. Viewing Available Clock Networks in Chip Planner
7.1.3.3. Viewing Clock Sector Utilization in Chip Planner
7.1.3.4. Viewing Routing Congestion in Chip Planner
7.1.3.5. Viewing I/O Banks in Chip Planner
7.1.3.6. Viewing High-Speed Serial Interfaces (HSSI) in Chip Planner
7.1.3.7. Viewing Source and Destination Nodes in Chip Planner
7.1.3.8. Viewing Fan-In and Fan-Out in Chip Planner
7.1.3.9. Viewing Immediate Fan-In and Fan-Out in Chip Planner
7.1.3.10. Viewing the Selected Contents in Chip Planner
7.1.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner
7.1.3.12. Viewing Module Placement by Cross-Probing to Chip Planner
7.2.1. The Logic Lock Regions Window
7.2.2. Defining Logic Lock Regions
7.2.3. Customizing the Shape of Logic Lock Regions
7.2.4. Assigning Device Pins to Logic Lock Regions
7.2.5. Viewing Connections Between Logic Lock Regions in Chip Planner
7.2.6. Example: Placement Best Practices for Intel® Arria® 10 FPGAs
7.2.7. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition
8.4.1. ECO Command Quick Reference
8.4.2. make_connection
8.4.3. remove_connection
8.4.4. modify_lutmask
8.4.5. adjust_pll_refclk
8.4.6. modify_io_slew_rate
8.4.7. modify_io_current_strength
8.4.8. modify_io_delay_chain
8.4.9. create_new_node
8.4.10. remove_node
8.4.11. place_node
8.4.12. unplace_node
8.4.13. create_wirelut
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6.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
The Intel® Quartus® Prime software generates a periphery to core placement and routing optimization summary in the Fitter (Place & Route) report after compilation.
- Compile your Intel® Quartus® Prime project.
- In the Tasks pane, select Compilation.
- Under Fitter (Place & Route), double-click View Report.
- In the Fitter folder, expand the Place Stage folder.
- Double-click Periphery to Core Transfer Optimization Summary.
Table 34. Fitter Report - Periphery to Core Transfer Optimization (P2C) Summary From Path To Path Status Node 1 Node 2 Placed and Routed—Core register is locked. Periphery to core/core to periphery routing is committed. Node 3 Node 4 Placed but not Routed—Core register is locked. Routing is not committed. This occurs when P2C is not able to optimize all targeted paths within a single group, for example, the same delay/wire requirement, or the same control signals. Partial P2C routing commitments may cause unresolvable routing congestion. Node 5 Node 6 Not Optimized—This occurs when P2C is set to Auto and the path is not optimized due to one of the following issues: - The delay requirement is impossible to achieve.
- The minimum delay requirement (for hold timing) is too large. The P2C algorithm cannot efficiently handle cases when many wires need to be added to meet hold timing.
- P2C encountered unresolvable routing congestion for this particular path.