Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

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ID 683641
Date 8/01/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Optimization Overview 3. Optimizing the Design Netlist 4. Netlist Optimizations and Physical Synthesis 5. Area Optimization 6. Timing Closure and Optimization 7. Analyzing and Optimizing the Design Floorplan 8. Using the ECO Compilation Flow 9. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Optimization Overview x
2.1. Initial FPGA Device Considerations 2.2. Initial Compiler Settings 2.3. Optimization Trade-Offs and Limitations 2.4. Design Visualization and Optimization Tools 2.5. Design Optimization Overview Revision History
2.1. Initial FPGA Device Considerations x
2.1.1. Device Migration Considerations
2.2. Initial Compiler Settings x
2.2.1. Initial I/O Assignment Guidelines 2.2.2. Initial Timing Constraint Guidelines
2.3. Optimization Trade-Offs and Limitations x
2.3.1. Area Reduction Trade-Offs 2.3.2. Critical Path Delay Reduction Trade-Offs 2.3.3. Power Consumption Reduction Trade-Offs 2.3.4. Compilation Time Trade-Offs
2.4. Design Visualization and Optimization Tools x
2.4.1. Design Visualization Tools 2.4.2. Design Optimization Tools
3. Optimizing the Design Netlist x
3.1. When to Use the Netlist Viewers: Analyzing Design Problems 3.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers 3.3. RTL Viewer Overview 3.4. Technology Map Viewer Overview 3.5. Netlist Viewer User Interface 3.6. Schematic View 3.7. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows 3.8. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows 3.9. Viewing a Timing Path 3.10. Optimizing the Design Netlist Revision History
3.3. RTL Viewer Overview x
3.3.1. Maximizing Readability in RTL Viewer 3.3.2. Running the RTL Viewer
3.5. Netlist Viewer User Interface x
3.5.1. Netlist Navigator Pane 3.5.2. Properties Pane 3.5.3. Netlist Viewers Find Pane
3.6. Schematic View x
3.6.1. Display Schematics in Multiple Tabbed View 3.6.2. Schematic Symbols 3.6.3. Select Items in the Schematic View 3.6.4. Shortcut Menu Commands in the Schematic View 3.6.5. Filtering in the Schematic View 3.6.6. View Contents of Nodes in the Schematic View 3.6.7. Moving Nodes in the Schematic View 3.6.8. View LUT Representations in the Technology Map Viewer 3.6.9. Zoom Controls 3.6.10. Navigating with the Bird's Eye View 3.6.11. Partition the Schematic into Pages 3.6.12. Follow Nets Across Schematic Pages
4. Netlist Optimizations and Physical Synthesis x
4.1. Physical Synthesis Optimizations 4.2. Applying Netlist Optimizations 4.3. Scripting Support 4.4. Netlist Optimizations and Physical Synthesis Revision History
4.1. Physical Synthesis Optimizations x
4.1.1. Disabling or Enabling Physical Synthesis Optimization 4.1.2. Physical Synthesis Options
4.2. Applying Netlist Optimizations x
4.2.1. WYSIWYG Primitive Resynthesis
4.3. Scripting Support x
4.3.1. Synthesis Netlist Optimizations 4.3.2. Physical Synthesis Optimizations
5. Area Optimization x
5.1. Resource Utilization Information 5.2. Optimizing Resource Utilization 5.3. Scripting Support 5.4. Area Optimization Revision History
5.1. Resource Utilization Information x
5.1.1. Flow Summary Report 5.1.2. Fitter Reports 5.1.3. Design Assistant Recommendations 5.1.4. Analysis and Synthesis Reports 5.1.5. Compilation Messages 5.1.6. Chip Planner Visualization
5.1.2. Fitter Reports x
5.1.2.1. Route Stage Reports
5.1.2.1. Route Stage Reports x
5.1.2.1.1. Nets with Highest Wire Count Report 5.1.2.1.2. Delay Chain Summary Report 5.1.2.1.3. Top Congested Hierarchies and Nets Reports 5.1.2.1.4. Global Route Reports
5.2. Optimizing Resource Utilization x
5.2.1. Resource Utilization Issues Overview 5.2.2. I/O Pin Utilization or Placement 5.2.3. Logic Utilization or Placement 5.2.4. Routing
5.2.2. I/O Pin Utilization or Placement x
5.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package
5.2.3. Logic Utilization or Placement x
5.2.3.1. Guideline: Optimize Source Code 5.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed 5.2.3.3. Guideline: Restructure Multiplexers 5.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 5.2.3.5. Guideline: Use Register Packing 5.2.3.6. Guideline: Remove Fitter Constraints 5.2.3.7. Guideline: Flatten the Hierarchy During Synthesis 5.2.3.8. Guideline: Re-target Memory Blocks 5.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area 5.2.3.10. Guideline: Retarget or Balance DSP Blocks 5.2.3.11. Guideline: Use a Larger Device 5.2.3.12. Guideline: Reduce Global Signal Congestion 5.2.3.13. Guideline: Report Pipelining Information
5.2.4. Routing x
5.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 5.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always 5.2.4.3. Guideline: Increase Router Effort Multiplier 5.2.4.4. Guideline: Remove Fitter Constraints 5.2.4.5. Guideline: Optimize Synthesis for Routability 5.2.4.6. Guideline: Optimize Source Code 5.2.4.7. Guideline: Use a Larger Device
5.3. Scripting Support x
5.3.1. Initial Compilation Settings 5.3.2. Resource Utilization Optimization Techniques
6. Timing Closure and Optimization x
6.1. Optimize Multi Corner Timing 6.2. Optimize Critical Paths 6.3. Optimize Critical Chains 6.4. Design Evaluation for Timing Closure 6.5. Timing Optimization 6.6. Periphery to Core Register Placement and Routing Optimization 6.7. Scripting Support 6.8. Timing Closure and Optimization Revision History
6.2. Optimize Critical Paths x
6.2.1. Viewing Critical Paths
6.3. Optimize Critical Chains x
6.3.1. Viewing Critical Chains
6.4. Design Evaluation for Timing Closure x
6.4.1. Review Messages 6.4.2. Evaluate Fitter Netlist Optimizations 6.4.3. Evaluate Optimization Results 6.4.4. Evaluate Resource Usage 6.4.5. Evaluate Other Reports and Adjust Settings Accordingly 6.4.6. Evaluate Clustering Difficulty 6.4.7. Revise and Recompile
6.4.4. Evaluate Resource Usage x
6.4.4.1. Evaluate Global and Non-Global Usage 6.4.4.2. Evaluate Routing Usage 6.4.4.3. Evaluate Wires Added for Hold
6.5. Timing Optimization x
6.5.1. Correct Design Assistant Rule Violations 6.5.2. Implement Fast Forward Timing Closure Recommendations 6.5.3. Review Timing Path Details 6.5.4. Try Optional Fitter Settings 6.5.5. Back-Annotate Optimized Assignments 6.5.6. Optimize Settings with Design Space Explorer II 6.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard 6.5.8. I/O Timing Optimization Techniques 6.5.9. Register-to-Register Timing Optimization Techniques 6.5.10. Metastability Analysis and Optimization Techniques
6.5.2. Implement Fast Forward Timing Closure Recommendations x
6.5.2.1. Retiming Limit Details Report 6.5.2.2. Fast Forward Timing Closure Recommendations
6.5.2.1. Retiming Limit Details Report x
6.5.2.1.1. Using the Retiming Limit Details Report
6.5.2.2. Fast Forward Timing Closure Recommendations x
6.5.2.2.1. Generating Fast Forward Timing Closure Recommendations 6.5.2.2.2. Implementing Fast Forward Recommendations
6.5.3. Review Timing Path Details x
6.5.3.1. Report Timing Setup Slack Breakdown On the Extra Info Tab 6.5.3.2. Report Logic Depth 6.5.3.3. Report Neighbor Paths 6.5.3.4. Report Register Spread 6.5.3.5. Report Route Net of Interest 6.5.3.6. Report Retiming Restrictions 6.5.3.7. Report Pipelining Information 6.5.3.8. Report CDC Viewer 6.5.3.9. Timing Closure Recommendations 6.5.3.10. Global Network Buffers 6.5.3.11. Resets and Global Networks 6.5.3.12. Suspicious Setup 6.5.3.13. Auto Shift Register Replacement 6.5.3.14. Clocking Architecture
6.5.3.10. Global Network Buffers x
6.5.3.10.1. Source Location 6.5.3.10.2. Insertion Delay 6.5.3.10.3. Fan-Out 6.5.3.10.4. Global Signal Assignment
6.5.4. Try Optional Fitter Settings x
6.5.4.1. Optimize Hold Timing 6.5.4.2. Fitter Aggressive Routability Optimization
6.5.6. Optimize Settings with Design Space Explorer II x
6.5.6.1. DSE II Computing Resources 6.5.6.2. DSE II Optimization Parameters 6.5.6.3. DSE II Result Management 6.5.6.4. Running DSE II
6.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard x
6.5.7.1. Aggregation Use Case 6.5.7.2. Comparison Use Case 6.5.7.3. Exploration Dashboard Object-Property Model 6.5.7.4. Starting the Exploration Dashboard
6.5.7.3. Exploration Dashboard Object-Property Model x
6.5.7.3.1. Base Exploration Dashboard Properties 6.5.7.3.2. Project Handle Properties 6.5.7.3.3. Project Group Objects and Properties 6.5.7.3.4. Workspace Objects and Properties
6.5.8. I/O Timing Optimization Techniques x
6.5.8.1. I/O Timing Constraints 6.5.8.2. Optimize IOC Register Placement for Timing Logic Option 6.5.8.3. Fast Input, Output, and Output Enable Registers 6.5.8.4. Programmable Delays 6.5.8.5. Use PLLs to Shift Clock Edges 6.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks 6.5.8.7. Spine Clock Limitations
6.5.9. Register-to-Register Timing Optimization Techniques x
6.5.9.1. Optimize Source Code 6.5.9.2. Improving Register-to-Register Timing 6.5.9.3. Physical Synthesis Optimizations 6.5.9.4. Set Power Optimization During Synthesis to Normal Compilation 6.5.9.5. Optimize Synthesis for Performance, Not Area 6.5.9.6. Flatten the Hierarchy During Synthesis 6.5.9.7. Set the Synthesis Effort to High 6.5.9.8. Change Adder Tree Styles 6.5.9.9. Duplicate Registers for Fan-Out Control 6.5.9.10. Prevent Shift Register Inference 6.5.9.11. Use Other Synthesis Options Available in Your Synthesis Tool 6.5.9.12. Fitter Seed 6.5.9.13. Set Maximum Router Timing Optimization Level 6.5.9.14. Register-to-Register Timing Analysis
6.5.9.9. Duplicate Registers for Fan-Out Control x
6.5.9.9.1. Manual Register Duplication 6.5.9.9.2. Automatic Register Duplication: Estimated Physical Proximity 6.5.9.9.3. Automatic Register Duplication: Hierarchical Proximity
6.5.9.14. Register-to-Register Timing Analysis x
6.5.9.14.1. Tips for Analyzing Failing Paths 6.5.9.14.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 6.5.9.14.3. Tips for Critical Path Analysis 6.5.9.14.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 6.5.9.14.5. Global Routing Resources 6.5.9.14.6. Register RAMS and DSPs
6.6. Periphery to Core Register Placement and Routing Optimization x
6.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box 6.6.2. Setting Periphery to Core Optimizations in the Assignment Editor 6.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
6.7. Scripting Support x
6.7.1. Initial Compilation Settings 6.7.2. I/O Timing Optimization Techniques 6.7.3. Register-to-Register Timing Optimization Techniques
7. Analyzing and Optimizing the Design Floorplan x
7.1. Design Floorplan Analysis in Chip Planner 7.2. Defining Logic Lock Placement Constraints 7.3. Defining Virtual Pins 7.4. Using Logic Lock Regions in Combination with Design Partitions 7.5. Creating Clock Region Assignments in Chip Planner 7.6. Scripting Support 7.7. Analyzing and Optimizing the Design Floorplan Revision History
7.1. Design Floorplan Analysis in Chip Planner x
7.1.1. Starting the Chip Planner 7.1.2. Chip Planner GUI 7.1.3. Viewing Design Elements in Chip Planner 7.1.4. Finding Design Elements in the Chip Planner 7.1.5. Exploring Paths in the Chip Planner 7.1.6. Viewing Assignments in the Chip Planner 7.1.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner 7.1.8. Viewing Design Partition Placement
7.1.3. Viewing Design Elements in Chip Planner x
7.1.3.1. Viewing Architecture-Specific Design Information in Chip Planner 7.1.3.2. Viewing Available Clock Networks in Chip Planner 7.1.3.3. Viewing Clock Sector Utilization in Chip Planner 7.1.3.4. Viewing Routing Congestion in Chip Planner 7.1.3.5. Viewing I/O Banks in Chip Planner 7.1.3.6. Viewing High-Speed Serial Interfaces (HSSI) in Chip Planner 7.1.3.7. Viewing Source and Destination Nodes in Chip Planner 7.1.3.8. Viewing Fan-In and Fan-Out in Chip Planner 7.1.3.9. Viewing Immediate Fan-In and Fan-Out in Chip Planner 7.1.3.10. Viewing the Selected Contents in Chip Planner 7.1.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner 7.1.3.12. Viewing Module Placement by Cross-Probing to Chip Planner
7.1.4. Finding Design Elements in the Chip Planner x
7.1.4.1. Find Options (Chip Planner Search)
7.1.5. Exploring Paths in the Chip Planner x
7.1.5.1. Analyzing Connections for a Path 7.1.5.2. Locate Path from the Timing Analysis Report to the Chip Planner 7.1.5.3. Show Delays 7.1.5.4. Viewing Routing Resources
7.2. Defining Logic Lock Placement Constraints x
7.2.1. The Logic Lock Regions Window 7.2.2. Defining Logic Lock Regions 7.2.3. Customizing the Shape of Logic Lock Regions 7.2.4. Assigning Device Pins to Logic Lock Regions 7.2.5. Viewing Connections Between Logic Lock Regions in Chip Planner 7.2.6. Example: Placement Best Practices for Intel® Arria® 10 FPGAs 7.2.7. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition
7.2.2. Defining Logic Lock Regions x
7.2.2.1. Defining a Logic Lock Region in Chip Planner 7.2.2.2. Defining a Logic Lock Region from the Project Navigator 7.2.2.3. Defining Routing Regions 7.2.2.4. Defining Empty Logic Lock Regions 7.2.2.5. Defining Hierarchical Logic Lock Regions
7.2.2.1. Defining a Logic Lock Region in Chip Planner x
7.2.2.1.1. Logic Lock Region Properties 7.2.2.1.2. Snapping to a Region 7.2.2.1.3. Considerations for Auto Sized Regions
7.2.3. Customizing the Shape of Logic Lock Regions x
7.2.3.1. Adding a New Shape to a Logic Lock Region 7.2.3.2. Subtracting Shape from Logic Lock Region 7.2.3.3. Merging Logic Lock Regions 7.2.3.4. Defining Noncontiguous Logic Lock Regions
7.4. Using Logic Lock Regions in Combination with Design Partitions x
7.4.1. Viewing Design Connectivity and Hierarchy
7.5. Creating Clock Region Assignments in Chip Planner x
7.5.1. Creating Clock Assignments in Chip Planner 7.5.2. Resizing a Clock Assignment in Chip Planner 7.5.3. Moving a Clock Assignment in Chip Planner 7.5.4. Deleting a Clock Region Assignment in Chip Planner 7.5.5. Assigning a Clock Signal to a Clock Region in Chip Planner
7.5.1. Creating Clock Assignments in Chip Planner x
7.5.1.1. Clock Assignment Properties
7.6. Scripting Support x
7.6.1. Creating Logic Lock Assignments with Tcl commands 7.6.2. Assigning Virtual Pins with a Tcl command 7.6.3. Logic Lock Region Assignment Examples
8. Using the ECO Compilation Flow x
8.1. ECO Compilation Flow 8.2. ECO Tcl Script Example 8.3. Viewing ECO Compilation Reports 8.4. ECO Commands 8.5. ECO Command Limitations 8.6. Interactive ECO Fitting 8.7. Using the ECO Compilation Flow Revision History
8.4. ECO Commands x
8.4.1. ECO Command Quick Reference 8.4.2. make_connection 8.4.3. remove_connection 8.4.4. modify_lutmask 8.4.5. adjust_pll_refclk 8.4.6. modify_io_slew_rate 8.4.7. modify_io_current_strength 8.4.8. modify_io_delay_chain 8.4.9. create_new_node 8.4.10. remove_node 8.4.11. place_node 8.4.12. unplace_node 8.4.13. create_wirelut
8.6. Interactive ECO Fitting x
8.6.1. eco_load_design and eco_commit_design Commands
1. Answers to Top FAQs
2. Design Optimization Overview
3. Optimizing the Design Netlist
4. Netlist Optimizations and Physical Synthesis
5. Area Optimization
6. Timing Closure and Optimization
7. Analyzing and Optimizing the Design Floorplan
8. Using the ECO Compilation Flow
9. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Intel® Quartus® Prime Pro Edition User Guides

6.5.3.1. Report Timing

The Timing Analyzer's Reports > Timing Slack > Report Timing… command allows you to specify settings to report the timing of any path or clock domain in the design. The equivalent scripting command is report_timing.

Figure 37. Report Timing Report

You can specify various options to customize the reporting. You can specify the Clocks and Targets that the report displays, the Analysis Type to run, whether to display Extra Info in the report, and the Output options for the report. For example, you can increase the number of paths to report, add a Target filter, and add a From Clock.

Figure 38. Report Timing Dialog Box (Top Section)
Figure 39. Report Timing Dialog Box (Bottom Section)
Table 15.  Report Timing Settings
Option Description
Clocks From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify.
Targets Specifies the target node for From Clock and To Clock to report paths with only those endpoints. Specify an I/O or register name or I/O port for this option. The field also supports wildcard characters. For example, to report only paths within a specific hierarchy:
report_timing -from *|egress:egress_inst|* \
     -to *|egress:egress_inst|* -(other options)
When the From, To, or Through boxes are empty, the Timing Analyzer assumes all possible targets in the device. The Through option limits the report to paths that pass through combinatorial logic, or a particular pin on a cell.
Analysis type The Analysis type options are Setup, Hold, Recovery, or Removal. The Timing Analyzer reports the results for the type of analysis you select.
Paths Specifies the number of paths to display by endpoint and slack level. The default value for Report number of paths is 10, otherwise, the report can be very long. Enable Pairs only to list only one path for each pair of source and destination. Limit further with Maximum number of paths per endpoints. You can also filter paths by entering a value in the Maximum slack limit field.
Extra Info Provides additional data that is relevant for diagnosing timing failure root cause, such as setup slack breakdown, and unexpected routing detours caused by congestion and hold time fix-up. Specify whether to include None, Basic, or All extra information in the report. The Extra Info tab data can help you identify potential, unnecessary routing detours, as well as placement or circuit issues that restrict the path fMAX performance. Refer to Setup Slack Breakdown On the Extra Info Tab.
  • All—report includes Extra Info tab that reports extra information for source timing endpoints that pass through the unregistered output of a RAM or DSP block, or for destination timing endpoints that pass through the unregistered input of a DSP block. The Data Path tab includes Estimated Delay Added for Hold and Route Stage Congestion Impact data.
  • Basic—report includes the Extra Info tab but no extra information on the Data Path tab.
  • None—report includes no Extra Info tab or other extra information on the Data Path tab.
Output Specify the path types the analysis includes in output for Detail level:
  • Summary—level includes basic summary reports. Review the Clock Skew column in the Summary report. If the skew is less than +/-150ps, the clock tree is well balanced between source and destination.
  • Path only—displays all the detailed information, except the Data Path tab displays the clock tree as one line item.
  • Path and Clock—displays the same as Path only with respect to the clock.
  • Full path—when higher clock skew is present, enable the Full path option. This option breaks the clock tree into greater detail, showing every cell, including the input buffer, PLL, global buffer (called CLKCTRL_), and any logic. Review this data to determine the cause of clock skew in your design. Use the Full path option for I/O analysis because only the source clock or destination clock is inside the FPGA, and therefore the delay is a critical factor to meet timing.
Show routing Shows routing data in the report.
Split the report by operating conditions For the operating condition timing corners, subdivides the data by each operating condition.
Report panel name Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name, you can Overwrite or Append the file with latest data.
Tcl command Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file.
Figure 40. Extra Info Tab

Setup Slack Breakdown On the Extra Info Tab

The Extra Info tab contains other timing metrics to help you diagnose timing closure issues, including Setup Slack Breakdown for the path.

The slack of a path specifies the margin by which the path meets its timing requirement. The setup slack breakdown is a numeric value that the Timing Analyzer calculates from the following timing requirements and path element delays:

Figure 41.  Setup Slack Breakdown Calculations

A path can fail timing requirements for many different reasons. For example, the clock relationship can be impossibly tight, or there can be excessive routing delays that alone cause failure for the timing path. Calculating the intrinsic margin of a timing path, and then comparing that margin to other delays of the path, can help identify the specific reasons why a path fails its timing requirement.

The Extra Info tab can help you identify potential significant or unexpected routing detours caused by congestion and hold time fix-up. The Extra Info tab can also report extra information for source timing endpoints that pass through the unregistered output of a RAM or DSP block, or for destination timing endpoints that pass through the unregistered input of a DSP block.

You can review the Extra Info data and Locate Path or Locate Chip Area in Chip Planner, Technology Map Viewer, or Resource Property Viewer to determine whether to make changes to improve placement and routing.

Some delay elements are more sensitive to a path’s placement and routing than others. Intrinsic delays that are part of Setup Slack Breakdown are less sensitive to placement and routing, and are inherent in the RTL and timing requirements. Non-intrinsic delays are the other delays that are sensitive to placement and routing.

Table 16.  Extra Info Tab Data
Extra Info Data Description
Intrinsic Margin

Reports the intrinsic and non-intrinsic timing elements that comprise the timing path slack value. Intrinsic margin is a numeric value that the Timing Analyzer calculates from the timing requirements and path element delays. The Timing Analyzer also derives the slack of the path from the same requirements and delays, but with a different calculation. Intrinsic delays are less sensitive to placement and routing, and are inherent in the RTL and timing requirements. Non-intrinsic delays are the other delays that are sensitive to placement and routing.

From Node Info Specifies the node Type, any Retiming Restriction, and any Power-Up "Don't Care" attributes for the From Node. Consider removing the retiming restriction to allow retiming and improve performance for timing closure.
To Node Info Specifies the node Type, any Retiming Restriction, and any Power-Up "Don't Care" attributes for the To Node. Consider removing the retiming restriction to allow retiming and improve performance for timing closure.
Max Fanout

Reports the maximum fan-out of register and combinational nodes in the path.

Route Stage Congestion Impact Reports whether routing has a Low, Medium, or High impact on congestion. A Low value suggests timing issues are not congestion related. A High value suggests competition for scarce routing resources plays a role in poor timing.
Estimated Delay Added for Hold Reports the estimated amount of delay added on to the fastest delay route to satisfy hold. This value can help you determine whether delays are routing congestion or Hold related.
Sufficient Setup Margin for Hold Reports whether the setup margin is suitable for the hold timing. Yes, indicates that the setup margin is sufficient. No indicates that the setup margin is insufficient for hold timing.
Source/Destination Bounding Box Reports the lower-left and upper-right coordinates for the boundary box enclosing the source and destination registers.

In an ideal case, the Source/Destination Bounding Box, Cell Bounding Box, and Interconnect Bounding Box values are roughly the same, and the relative areas are approximately 1.0. If the cell bounding box size grows relative to the Source/Destination Bounding Box, that can indicate a potential unnecessary routing detour on the path.

Source/Destination Area Covered Reports the total area covered in terms of LABs.
Source/Destination Relative Area Reports the area for the source and destination, relative to the Source/Destination Bounding Box. The value is always 1.0, which equals the same size.
Cell Bounding Box Reports the lower-left and upper-right coordinates for the boundary box enclosing the source and destination registers, and any cells in the path.
Cell Area Covered Reports the area for the cell, relative to the Source/Destination Bounding Box. A value of 1.0 equals the same size. A value greater than 1.0 can indicate a path has a cell outside of the space between the registers in the path.

The following describe the interpretation of timing conditions indicated by the Setup Slack Breakdown:

  • When the Setup Slack Breakdown is less than 0—the path has such a tight timing relationship, a large difference in microparameters, or such significant clock source uncertainty, that the path fails before the addition of any delay. Review the SDC constraints to verify that the timing relationship is correct. An incorrect relationship can exist between unrelated clocks that lack the proper timing cut. Ensure that parameterizable hard blocks (such as 20K RAM and DSP blocks) are fully registered. Investigate clock sources to verify that the clocks use global signals for routing.
  • When the clock skew exceeds the Setup Slack Breakdown —address the clock transfer to meet timing on the path. You may need to create clock region assignments. You might also need to redesign cross-clock transfers to switch from synchronous to asynchronous implementation, such as with a FIFO or other handshake.
  • When the cell delay is greater than its intrinsic margin—reduce the cell delay, as the path would fail timing even if the clocks are perfect and use no routing wires. Rewrite RTL to reduce the logic depth, restructure logic to allow the Compiler to use faster LUT inputs, or unblock retiming optimizations. The Compiler can automatically retime registers to reduce logic depth, but only in ways that maintain functionality and that the device architecture supports. To unblock the Hyper-Retimer, remove asynchronous resets and initial conditions.
  • When the interconnect delay is greater than its intrinsic margin—the path would fail timing even if the clocks are perfect, and there is no logic. This occurs if registers are too far apart, or a timing path detours around a congested chip area. Review the fan-in and fan-out of registers that are far apart. Apply Logic Lock regions so the Fitter places the registers closer together. Use Logic Lock regions only after determining why placement is initially poor.
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