Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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2.18.3.1. Generating a Simulation Registration Include File (Optional Early RTL Simulation Flow)

To generate a simulation registration include file for the optional early RTL simulation flow, follow these steps:

  1. Connect the AXI4 NoC manager ports to the AXI4 NoC subordinate ports in the System View tab of Platform Designer. The AXI4 NoC manager ports are on the NoC Initiator Intel FPGA IP. The AXI4 NoC subordinate ports are on the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP and on the External Memory Interfaces Intel Agilex® 7 Intel FPGA IP.
  2. Click the Address Map tab in Platform Designer to assign starting addresses for each NoC initiator to target connection. If an initiator connects to multiple targets, ensure that each target has a unique starting address. The end address is auto calculated based on the memory span.
  3. Save you system and click Generate HDL. Platform Designer generates the registration include file along with the HDL. There is no need to run Analysis & Elaboration before simulation when using this flow.