Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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4.3.8.2. Analyze Synthesis Files in the Platform Designer Component Editor

After you specify the top-level HDL file in the Platform Designer Component Editor, click Analyze Synthesis Files to analyze the parameters and signals in the top-level, and then select the top-level module from the Top Level Module list. If there is a single module or entity in the HDL file, Platform Designer automatically populates the Top-level Module list.

Once analysis is complete and the top-level module is selected, you can view the parameters and signals on the Parameters and Signals & Interfaces tabs. The Component Editor may report errors or warnings at this stage, because the signals and interfaces are not yet fully defined.

Note: At this stage in the Component Editor flow, you cannot add or remove parameters or signals created from a specified HDL file without editing the HDL file itself.

The synthesis files are added to a fileset with the name QUARTUS_SYNTH and type QUARTUS_SYNTH in the _hw.tcl file created by the Component Editor. The top-level module is used to specify the TOP_LEVEL fileset property. Each synthesis file is individually added to the fileset. If the source files are saved in a different directory from the working directory where the _hw.tcl is located, you can use standard fixed or relative path notation to identify the file location for the PATH variable.

_hw.tcl Created from Entries in the Files tab in the Synthesis Files Section

# file sets

add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL demo_axi_memory

add_fileset_file demo_axi_memory.sv 
SYSTEM_VERILOG PATH demo_axi_memory.sv

add_fileset_file single_clk_ram.v VERILOG PATH single_clk_ram.v