Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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6.1.9.3. Burst Adaptation: Avalon® to AXI

The following entries specify the behavior when converting between Avalon® and AXI burst types.

Note: The Platform Designer-generated interconnect that adapts between an Avalon® memory-mapped interface host and a connected AXI subordinate does not account for the AXI3 or AXI4 4KB boundary restriction for burst transactions. When connecting an Avalon® memory-mapped interface FPGA host to an AXI subordinate in Platform Designer, you must ensure that the bursts do not exceed the AXI3 or AXI4 4KB boundary restriction for burst transactions.
Table 45.  Burst Adaptation: Avalon® to AXI
Burst Type Definition
Sequential Bursts of length greater than 16 are converted to multiple INCR bursts of a length less than or equal to 16. Bursts of length less than or equal to 16 are not converted.
Wrapping Only Avalon® hosts with alwaysBurstMaxBurst = true are supported. The WRAP burst is passed through if the length is less than or equal to 16. Otherwise, it is converted to two or more INCR bursts that respect the transaction's wrap boundary.
GENERIC_CONVERTER Controls all burst conversions with a single converter that adapts all incoming burst types, resulting in an adapter that has smaller area, but lower fMAX.