Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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5.10.1.1. Avalon Pipelined Read Host Example Design Requirements

You must carefully design the logic for the control and datapaths of pipelined read hosts. The control logic must extend a read cycle whenever the waitrequest signal is asserted. This logic must also control the host address, byteenable, and read signals. To achieve maximum throughput, pipelined read hosts should post reads continuously while waitrequest is deasserted. While read is asserted, the address presented to the interconnect is stored.

The datapath logic includes the readdata and readdatavalid signals. If your host can accept data on every clock cycle, you can register the data with the readdatavalid as an enable bit. If your host cannot process a continuous stream of read data, it must buffer the data in a FIFO. The control logic must stop issuing reads when the FIFO reaches a predetermined fill level to prevent FIFO overflow.