Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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2.8.3. Connecting NoC IP in Platform Designer

Intel Agilex® 7 M-Series FPGAs support an integrated Network-on-Chip (NoC) to facilitate high-bandwidth data movement between the FPGA core logic and memory resources, such as HBM2e and DDR5 memories.

In the regular NoC compilation flow, you specify connections between NoC IP in the NoC Assignment Editor after running Analysis & Elaboration. You also specify address mapping and performance requirements for these connections in the NoC Assignment Editor. These assignments are required to perform RTL simulation of your design.

An optional early RTL simulation flow is available where you can specify NoC IP connection and addressing in Platform Designer. In this early simulation flow, you can perform RTL simulation after generating HDL for your Platform Designer system, but before running Analysis & Elaboration and making assignments in NoC Assignment Editor.

Note: If you use this early RTL simulation flow, you must still run Analysis & Elaboration and make connection and addressing assignments in NoC Assignment Editor before performing compilation.

If you want to enable early RTL simulation for your design, follow the steps below to specify NoC IP connectivity and addressing in Platform Designer. If you run Analysis & Elaboration and use the NoC Assignment Editor to make these assignments before running simulation, these steps are unnecessary.

  1. Connect the AXI4 NoC manager ports to appropriate AXI4 NoC subordinate ports in the Platform Designer System View tab. The AXI4 NoC manager ports are on the NoC Initiator Intel FPGA IP. The AXI4 NoC subordinate ports are on the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP and on the External Memory Interfaces Intel Agilex® 7 Intel FPGA IP.
  2. Click the Address Map tab in Platform Designer to assign starting addresses for each NoC initiator to target connection. If an initiator connects to multiple targets, ensure that each target has a unique starting address. The end address is auto calculated based on the memory span.
  3. Save you system and click Generate HDL. Platform Designer stores the NoC connectivity and addressing as assignments in the project .qsf.
    Note: This connectivity and addressing is not present in the HDL netlist that Platform Designer generates.

When using the Platform Designer flow for specifying NoC connectivity and addressing, the design is ready for RTL simulation after generating HDL for the Platform Designer system. For details on simulation, refer to Generating Simulation Files NoC Designs and also to Intel Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.