DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements 1.3. Generating the DisplayPort Intel® FPGA IP Design Example 1.4. Simulating the Design 1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design x
1.5.1. Regenerating .elf File
2. Parallel Loopback Design Examples x
2.1. Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features 2.4. Enabling Adaptive Sync Support 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameter 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features x
2.3.1. Cyclone® 10 GX DisplayPort SST TX-only Design Features 2.3.2. Cyclone® 10 GX DisplayPort SST RX-only Design Features
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

2. Parallel Loopback Design Examples

The DisplayPort Intel® FPGA IP Parallel Loopback design examples demonstrates parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Table 7.   DisplayPort Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST TX-only DisplayPort SST HBR3, HBR2, HBR, RBR Simplex —
DisplayPort SST RX-only DisplayPort SST HBR3, HBR2, HBR, RBR Simplex —
DisplayPort SST parallel loopback with PCR DisplayPort SST HBR3, HBR2, HBR, RBR Simplex Parallel with PCR
DisplayPort SST parallel loopback without PCR DisplayPort SST HBR3, HBR2, HBR, RBR Simplex Parallel without PCR
DisplayPort MST parallel loopback with PCR DisplayPort MST HBR3, HBR2, HBR, RBR Simplex Parallel with PCR
DisplayPort MST parallel loopback without PCR DisplayPort MST HBR3, HBR2, HBR, RBR Simplex Parallel without PCR

Section Content
Cyclone 10 GX DisplayPort SST Parallel Loopback Design Features
Cyclone 10 GX DisplayPort MST Parallel Loopback Design Features
Cyclone 10 GX DisplayPort SST TX-only or RX-only Design Features
Enabling Adaptive Sync Support
Design Components
Clocking Scheme
Interface Signals and Parameter
Hardware Setup
Simulation Testbench
DisplayPort Transceiver Reconfiguration Flow
Transceiver Lane Configurations

Level Two Title